Search Results - "Proceedings - International Test Conference"

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  1. 1
    Proceedings International Test Conference 1994

    Proceedings International Test Conference 1994

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  2. 2
    On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing

    On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing by Weichi Ding, Mingde Pan, Wong, W., Chow, D., Li, M. P., Shumarayev, S.

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  3. 3
    A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation

    A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation by Mongelli, Gianmarco, Faehn, Eric, Robins, Dylan, Girard, Patrick, Virazel, Arnaud

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  4. 4
    Generation and Quality Evaluation of Synthetic Process Control Monitoring Data

    Generation and Quality Evaluation of Synthetic Process Control Monitoring Data by Nigh, Matthew, Carulli, John, Makris, Yiorgos

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  5. 5
    Virtual Test Development Using Pre-Silicon Verification Environment

    Virtual Test Development Using Pre-Silicon Verification Environment by Aderholz, E., Atol, Q., Baptist, B., Holzner, R., Ignacio, R., Kamanuri, V., Kun, A., Ma, K., Mariacher, B., Pfabigan, O., Przybilla, A., Samardzic, D., Schlagbauer, F., Schleicher, M., Valiente, J.P., Vargas, E., Vinod, K., Zikulnig, O.

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  6. 6
    Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test

    Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test by Lai, Chi, Huang, Shi-Yu

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  7. 7
    Power-Aware Test Scheduling for Memory BIST

    Power-Aware Test Scheduling for Memory BIST by Au, Albert, Kcpinski, Michal, Orczyk, Makary, Pogiel, Artur

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  8. 8
    Test Data Encryption with a New Stream Cipher

    Test Data Encryption with a New Stream Cipher by Rajski, Janusz, Trawka, Maciej, Tyszer, Jerzy, Wlodarczak, Bartosz

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  9. 9
    Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects

    Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects by Zhang, Zhe, Mayahinia, Mahta, Weis, Christian, Wehn, Norbert, Tahoori, Mehdi, Nassif, Sani, Tshagharyan, Grigor, Harutyunyan, Gurgen, Zorian, Yervant

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  10. 10
    Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests

    Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests by Goel, Sandeep Kumar, Khan, Moiz, Patidar, Ankita, Lee, Frank, Nguyen, Vuong, Shankaranarayanan, Bharath, Kim, Doo, Arora, Manish

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  11. 11
    E-SCOUT: Efficient-Spatial Clustering-based Outlier Detection through Telemetry

    E-SCOUT: Efficient-Spatial Clustering-based Outlier Detection through Telemetry by Ortega, Eduardo, Talukdar, Jonti, Paik, Woohyun, Su, Fei, Chattopadhyay, Rita, Chakrabarty, Krishnendu

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  12. 12
    Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage

    Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage by Cheng, Wu-Tung, Sharma, Manish, Yang, Xin, Stelmach, Artur, Urban, Szczepan, Janicki, Jakub, McWithey, Preston

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  13. 13
    WM-Graph: Graph-Based Approach for Wafermap Analytics

    WM-Graph: Graph-Based Approach for Wafermap Analytics by Yang, Min Jian, Zeng, Yueling Jenny, Wang, Li-C.

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  14. 14
    Safety-Guided Test Generation for Structural Faults

    Safety-Guided Test Generation for Structural Faults by Tan, Xuanyi, Thapar, Dhruv, Sahoo, Deepesh, Chaudhuri, Arjun, Banerjee, Sanmitra, Chakrabarty, Krishnendu, Parekhji, Rubin

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  15. 15
    Electrical Stimulus Based Calibration of MEMS Accelerometer

    Electrical Stimulus Based Calibration of MEMS Accelerometer by Bassi, Ishaan, Ozev, Sule

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  16. 16
    Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant

    Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant by Li, Shu-Wen, Yen, Chia-Heng, Chang, Shuo-Wen, Chu, Ying-Hua, Wu, Kai-Chiang, Chao, Mango Chia-Tso

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  17. 17
    Design-for-Test for Silicon Photonic Circuits

    Design-for-Test for Silicon Photonic Circuits by Agnihotri, Pratishtha, Kalla, Priyank, Blair, Steve

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  18. 18
    qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors

    qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors by Li, Yen-Wei, Hsieh, Cheng-Yun, Wu, Meng-Chen, Li, James Chien-Mo

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  19. 19
    Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor

    Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor by Natarajan, Suriyaprakash, Oak, Chaitali S., Kakollu, Vijay, Chaplot, Nipun, Roy, Soham, Lonkar, Apurva, Reyes, Gerardo J. Perfecto

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  20. 20
    Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs

    Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs by Xun, Hanzhi, Fieback, Moritz, Yaldagard, Mohammad Amin, Yuan, Sicong, Hua, Erbing, Aziza, Hassen, Taouil, Mottaqiallah, Hamdioui, Said

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