Search Results - "Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques"

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  1. 1
    Modeling superscalar processors via statistical simulation

    Modeling superscalar processors via statistical simulation by Nussbaum, S., Smith, J.E.

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  2. 2
    Reactive-associative caches

    Reactive-associative caches by Batson, B., Vijaykumar, T.N.

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  3. 3
    Filtering techniques to improve trace-cache efficiency

    Filtering techniques to improve trace-cache efficiency by Rosner, R., Mendelson, A., Ronen, R.

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  4. 4
    Multi-chain prefetching: effective exploitation of inter-chain memory parallelism for pointer-chasing codes

    Multi-chain prefetching: effective exploitation of inter-chain memory parallelism for pointer-chasing codes by Kohout, N., Seungryul Choi, Dongkeun Kim, Yeung, D.

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    Optimizing software data prefetches with rotating registers

    Optimizing software data prefetches with rotating registers by Doshi, G., Krishnaiyer, R., Muthukumar, K.

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    Architectural support for parallel reductions in scalable shared-memory multiprocessors

    Architectural support for parallel reductions in scalable shared-memory multiprocessors by Garzaran, M.J., Prvulovic, M., Ye Zhang, Jula, A., Hao Yu, Rauchwerger, L., Torrellas, J.

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  7. 7
    Compiling for the Impulse memory controller

    Compiling for the Impulse memory controller by Xianglong Huang, Zhenlin Wang, McKinley, K.S.

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  8. 8
    A cost framework for evaluating integrated restructuring optimizations

    A cost framework for evaluating integrated restructuring optimizations by Chandramouli, B., Carter, J.B., Hsieh, W.C., McKee, S.A.

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  9. 9
    Boolean formula-based branch prediction for future technologies

    Boolean formula-based branch prediction for future technologies by Jimenez, D.A., Hanson, H.L., Lin, C.

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  10. 10
    Exploring the design space of future CMPs

    Exploring the design space of future CMPs by Jaehyuk Huh, Burger, D., Keckler, S.W.

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  11. 11
    Data flow analysis for software prefetching linked data structures in Java

    Data flow analysis for software prefetching linked data structures in Java by Cahoon, B., McKinley, K.S.

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  12. 12
    A unified modulo scheduling and register allocation technique for clustered processors

    A unified modulo scheduling and register allocation technique for clustered processors by Codina, J.M., Sanchez, J., Gonzalez, A.

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  13. 13
    Area and system clock effects on SMT/CMP processors

    Area and system clock effects on SMT/CMP processors by Burns, J., Gaudiot, J.-L.

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  14. 14
    Using dataflow based context for accurate value prediction

    Using dataflow based context for accurate value prediction by Thomas, R., Franklin, M.

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  15. 15
    Comparing and combining read miss clustering and software prefetching

    Comparing and combining read miss clustering and software prefetching by Pai, V.S., Adve, S.V.

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  16. 16
    Compiler and runtime analysis for efficient communication in data intensive applications

    Compiler and runtime analysis for efficient communication in data intensive applications by Ferreira, R., Agrawal, G., Saltzt, J.

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  17. 17
    Code reordering and speculation support for dynamic optimization systems

    Code reordering and speculation support for dynamic optimization systems by Nystrom, E.M., Barnes, R.D., Merten, M.C., Hwu, W.W.

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  18. 18
    Implementation and evaluation of the Complex Streamed Instruction set

    Implementation and evaluation of the Complex Streamed Instruction set by Juurlink, B., Tcheressiz, D., Vassiliadis, S., Wijshoff, H.A.G.

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  19. 19
    Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications

    Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications by Sherwood, Timothy, Perelman, Erez, Calder, Brad

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  20. 20
    Adaptive Mode Control: A Static-Power-Efficient Cache Design

    Adaptive Mode Control: A Static-Power-Efficient Cache Design by Zhou, Huiyang, Toburen, Mark C., Rotenberg, Eric, Conte, Thomas M.

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