Search Results - "Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)"

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  1. 1
    Task scheduling and voltage selection for energy minimization

    Task scheduling and voltage selection for energy minimization by Yumin Zhang, Xiaobo Hu, Chen, D.Z.

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  2. 2
    A universal technique for fast and flexible instruction-set architecture simulation

    A universal technique for fast and flexible instruction-set architecture simulation by Nohl, A., Braun, G., Schliebusch, O., Leupers, R., Meyr, H., Hoffmann, A.

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  3. 3
    Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

    Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique by Anis, M., Areibi, S., Mahmoud, M., Elmasry, M.

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  4. 4
    Analysis of power consumption on switch fabrics in network routers

    Analysis of power consumption on switch fabrics in network routers by Ye, T.T., Benini, L., De Micheli, G.

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  5. 5
    Compiler-directed scratch pad memory hierarchy design and management

    Compiler-directed scratch pad memory hierarchy design and management by Kandemir, M., Choudhary, A.

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  6. 6
    Dynamic hardware plugins in an FPGA with partial run-time reconfiguration

    Dynamic hardware plugins in an FPGA with partial run-time reconfiguration by Horta, E.L., Lockwood, J.W., Taylor, D.E., Parlour, D.

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  7. 7
    Traffic analysis for on-chip networks design of multimedia applications

    Traffic analysis for on-chip networks design of multimedia applications by Varatkar, G., Marculescu, R.

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  8. 8
    Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

    Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver by Ganai, M.K., Lintao Zhang, Ashar, P., Gupta, A., Malik, S.

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  9. 9
    Few electron devices: towards hybrid CMOS-SET integrated circuits

    Few electron devices: towards hybrid CMOS-SET integrated circuits by Ionescu, A.M., Declercq, M.J., Mahapatra, S., Banerjee, K., Gautier, J.

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  10. 10
    On output response compression in the presence of unknown output values

    On output response compression in the presence of unknown output values by Pomeranz, I., Kundu, S., Reddy, S.M.

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  11. 11
    Exploiting shared scratch pad memory space in embedded multiprocessor systems

    Exploiting shared scratch pad memory space in embedded multiprocessor systems by Kandemir, M., Ramanujam, J., Choudhary, A.

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  12. 12
    False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

    False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation by Jing-Jia Liou, Krstic, A., Wang, L.-C., Kwang-Ting Cheng

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  13. 13
    Guaranteed passive balancing transformations for model order reduction

    Guaranteed passive balancing transformations for model order reduction by Phillips, J., Daniel, L., Miguel Silveira, L.

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  14. 14
    System design methodologies for a wireless security processing platform

    System design methodologies for a wireless security processing platform by Ravi, S., Raghunathan, A., Potlapally, N., Sankaradass, M.

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  15. 15
    Uncertainty-aware circuit optimization

    Uncertainty-aware circuit optimization by Xiaoliang Bai, Visweswariah, C., Strenski, P.N., Hathaway, D.J.

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  16. 16
    Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs

    Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs by Iyengar, V., Chakrabarty, K., Marinissen, E.J.

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  17. 17
    Remembrance of circuits past: macromodeling by data mining in large analog design spaces

    Remembrance of circuits past: macromodeling by data mining in large analog design spaces by Hongzhou Liu, Singhee, A., Rutenbar, R.A., Carley, L.R.

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  18. 18
    DRG-cache: a data retention gated-ground cache for low power

    DRG-cache: a data retention gated-ground cache for low power by Agarwal, A., Hai Li, Roy, K.

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  19. 19
    The wearable motherboard: a framework for personalized mobile information processing (PMIP)

    The wearable motherboard: a framework for personalized mobile information processing (PMIP) by Sungmee Park, Mackenzie, K., Jayaraman, S.

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  20. 20
    An integer linear programming based approach for parallelizing applications in on-chip multiprocessors

    An integer linear programming based approach for parallelizing applications in on-chip multiprocessors by Kadayif, I., Kandemir, M., Sezer, U.

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