Search Results - "Proceedings of the 27th annual International Symposium on Computer Architecture"

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  1. 41
    Memory access scheduling

    Memory access scheduling by Rixner, Scott, Dally, William J., Kapasi, Ujval J., Mattson, Peter, Owens, John D.

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  2. 42
    Completion time multiple branch prediction for enhancing trace cache performance

    Completion time multiple branch prediction for enhancing trace cache performance by Rakvic, Ryan, Black, Bryan, Shen, John Paul

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  3. 43
    Energy-credit scheduler: An energy-aware virtual machine scheduler for cloud systems

    Energy-credit scheduler: An energy-aware virtual machine scheduler for cloud systems by Kim, Nakku, Cho, Jungwook, Seo, Euiseong

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  4. 44
    DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses

    DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses by Steiner, Lukas, Jung, Matthias, Prado, Felipe S., Bykov, Kirill, Wehn, Norbert

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  5. 45
    Selective register-file cache: an energy saving technique for embedded processor architecture

    Selective register-file cache: an energy saving technique for embedded processor architecture by Gudaparthi, Sumanth, Shrestha, Rahul

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  6. 46
    Exascale design space exploration and co-design

    Exascale design space exploration and co-design by Dosanjh, S.S., Barrett, R.F., Doerfler, D.W., Hammond, S.D., Hemmert, K.S., Heroux, M.A., Lin, P.T., Pedretti, K.T., Rodrigues, A.F., Trucano, T.G., Luitjens, J.P.

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  7. 47
    Layered Green Performance Indicators

    Layered Green Performance Indicators by Kipp, Alexander, Jiang, Tao, Fugini, Mariagrazia, Salomie, Ioan

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  8. 48
    A Collaborative CPU Vector Offloader: Putting Idle Vector Resources to Work on Commodity Processors

    A Collaborative CPU Vector Offloader: Putting Idle Vector Resources to Work on Commodity Processors by Son, Youngbin, Kang, Seokwon, Um, Hongjun, Lee, Seokho, Ham, Jonghyun, Kim, Donghyeon, Park, Yongjun

    Published in Electronics (Basel)
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  9. 49
    DAFT: Decoupled Acyclic Fault Tolerance

    DAFT: Decoupled Acyclic Fault Tolerance by Zhang, Yun, Lee, Jae W., Johnson, Nick P., August, David I.

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  10. 50
    Addressing isolation challenges of non-blocking caches for multicore real-time systems

    Addressing isolation challenges of non-blocking caches for multicore real-time systems by Valsan, Prathap Kumar, Yun, Heechul, Farshchi, Farzad

    Published in Real-time systems
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  11. 51
    RedThreads: An Interface for Application-Level Fault Detection/Correction Through Adaptive Redundant Multithreading

    RedThreads: An Interface for Application-Level Fault Detection/Correction Through Adaptive Redundant Multithreading by Hukerikar, Saurabh, Teranishi, Keita, Diniz, Pedro C., Lucas, Robert F.

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  12. 52
    A comparative simulation study on the power–performance of multi-core architecture

    A comparative simulation study on the power–performance of multi-core architecture by Saravanan, Vijayalakshmi, Anpalagan, Alagan, Kothari, D. P., Woungang, Isaac, Obaidat, Mohammad S.

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  13. 53
    Converging to periodic schedules for cyclic scheduling problems with resources and deadlines

    Converging to periodic schedules for cyclic scheduling problems with resources and deadlines by Dupont de Dinechin, Benoît, Munier Kordon, Alix

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  14. 54
    HTC-Sim: a trace-driven simulation framework for energy consumption in high-throughput computing systems

    HTC-Sim: a trace-driven simulation framework for energy consumption in high-throughput computing systems by Forshaw, M., McGough, A.S., Thomas, N.

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  15. 55
    The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

    The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration by Grüttner, Kim, Hartmann, Philipp A., Hylla, Kai, Rosinger, Sven, Nebel, Wolfgang, Herrera, Fernando, Villar, Eugenio, Brandolese, Carlo, Fornaciari, William, Palermo, Gianluca, Ykman-Couvreur, Chantal, Quaglia, Davide, Ferrero, Francisco, Valencia, Raúl

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  16. 56
    Region-based dual bank register allocation for reduced instruction encoding Architectures

    Region-based dual bank register allocation for reduced instruction encoding Architectures by Lee, Je-Hyung, Moon, Soo-Mook, Park, Jinpyo

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  17. 57
    A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

    A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations by Zoni, Davide, Terraneo, Federico, Fornaciari, William

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  18. 58
    Whole procedure heterogeneous multiprocessors low-power optimization at algorithm-level

    Whole procedure heterogeneous multiprocessors low-power optimization at algorithm-level by Wang, Zhuowei, Xiong, Naixue, Wang, Hao, Cheng, Lianglun, Zhao, Wuqing

    Published in Cluster computing
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  19. 59
    Energy-aware hybrid precision selection framework for mobile GPUs

    Energy-aware hybrid precision selection framework for mobile GPUs by Hsiao, Chih-Chieh, Chu, Slo-Li, Chen, Chen-Yu

    Published in Computers & graphics
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  20. 60
    The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUs

    The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUs by Liu, Wenjie, Ma, Sheng, Huang, Libo, Wang, Zhiying

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