Search Results - "Proceedings of the 27th annual International Symposium on Computer Architecture"

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    Proceedings of the 27th annual international symposium on Computer architecture

    Proceedings of the 27th annual international symposium on Computer architecture

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  2. 2
    A fully associative software-managed cache design

    A fully associative software-managed cache design by Hallnor, Erik G., Reinhardt, Steven K.

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    Memory access scheduling

    Memory access scheduling by Rixner, Scott, Dally, William J., Kapasi, Ujval J., Mattson, Peter, Owens, John D.

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    Transient fault detection via simultaneous multithreading

    Transient fault detection via simultaneous multithreading by Reinhardt, Steven K., Mukherjee, Shubhendu S.

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    Clock rate versus IPC: the end of the road for conventional microarchitectures

    Clock rate versus IPC: the end of the road for conventional microarchitectures by Agarwal, Vikas, Hrishikesh, M. S., Keckler, Stephen W., Burger, Doug

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    Energy-driven integrated hardware-software optimizations using SimplePower

    Energy-driven integrated hardware-software optimizations using SimplePower by Vijaykrishnan, N., Kandemir, M., Irwin, M. J., Kim, H. S., Ye, W.

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    Reconfigurable caches and their application to media processing

    Reconfigurable caches and their application to media processing by Ranganathan, Parthasarathy, Adve, Sarita, Jouppi, Norman P.

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    Piranha: a scalable architecture based on single-chip multiprocessing

    Piranha: a scalable architecture based on single-chip multiprocessing by Barroso, Luiz André, Gharachorloo, Kourosh, McNamara, Robert, Nowatzyk, Andreas, Qadeer, Shaz, Sano, Barton, Smith, Scott, Stets, Robert, Verghese, Ben

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    Multiple-banked register file architectures

    Multiple-banked register file architectures by Cruz, José-Lorenzo, González, Antonio, Valero, Mateo, Topham, Nigel P.

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    Architectural support for scalable speculative parallelization in shared-memory multiprocessors

    Architectural support for scalable speculative parallelization in shared-memory multiprocessors by Cintra, Marcelo, Martínez, José F., Torrellas, Josep

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    A scalable approach to thread-level speculation

    A scalable approach to thread-level speculation by Steffan, J. Greggory, Colohan, Christopher B., Zhai, Antonia, Mowry, Todd C.

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    Wattch: a framework for architectural-level power analysis and optimizations

    Wattch: a framework for architectural-level power analysis and optimizations by Brooks, David, Tiwari, Vivek, Martonosi, Margaret

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    On the value locality of store instructions

    On the value locality of store instructions by Lepak, Kevin M., Lipasti, Mikko H.

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    HLS: combining statistical and symbolic simulation to guide microprocessor designs

    HLS: combining statistical and symbolic simulation to guide microprocessor designs by Oskin, Mark, Chong, Frederic T., Farrens, Matthew

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    Understanding the backward slices of performance degrading instructions

    Understanding the backward slices of performance degrading instructions by Zilles, Craig B., Sohi, Gurindar S.

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    Recency-based TLB preloading

    Recency-based TLB preloading by Saulsbury, Ashley, Dahlgren, Fredrik, Stenström, Per

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    Vector instruction set support for conditional operations

    Vector instruction set support for conditional operations by Smith, J. E., Faanes, Greg, Sugumar, Rabin

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    Circuits for wide-window superscalar processors

    Circuits for wide-window superscalar processors by Henry, Dana S., Kuszmaul, Bradley C., Loh, Gabriel H., Sami, Rahul

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    Performance analysis of the Alpha 21264-based Compaq ES40 system

    Performance analysis of the Alpha 21264-based Compaq ES40 system by Cvetanovic, Zarka, Kessler, R. E.

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    Allowing for ILP in an embedded Java processor

    Allowing for ILP in an embedded Java processor by Radhakrishnan, Ramesh, Talla, Deependra, John, Lizy Kurian

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