Search Results - 정덕균

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  1. 1
    Design of a Transceiver Transmitting Power, Clock, and Data over a Single Optical Fiber for Future Automotive Network System

    Design of a Transceiver Transmitting Power, Clock, and Data over a Single Optical Fiber for Future Automotive Network System by Bae, Woorham, Ju, Haram, Jeong, Deog-Kyoon

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  2. 2
    0.11-2.5 GHz All-digital DLL for Mobile Memory Interface with Phase Sampling Window Adaptation to Reduce Jitter Accumulation

    0.11-2.5 GHz All-digital DLL for Mobile Memory Interface with Phase Sampling Window Adaptation to Reduce Jitter Accumulation by 채주형, 김민오, 홍기문, 박지환, 고형준, 신우열, 지한규, 정덕균, 김수환

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  3. 3
    A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

    A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL by Kavala, Anil, Bae, Woorham, Kim, Sungwoo, Hong, Gi-Moon, Chi, Hankyu, Kim, Suhwan, Jeong, Deog-Kyoon

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  4. 4
    A Digital Readout IC with Digital Offset Canceller for Capacitive Sensors

    A Digital Readout IC with Digital Offset Canceller for Capacitive Sensors by Lim, Dong-Hyuk, Lee, Sang-Yoon, Choi, Woo-Seok, Park, Jun-Eun, Jeong, Deog-Kyoon

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  5. 5
    A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

    A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring by Yoo, Byoung-Joo, Song, Ho-Young, Chi, Han-Kyu, Bae, Woo-Rham, Jeong, Deog-Kyoon

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  6. 6
    A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters

    A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters by Song, Hee-Soo, Kim, Su-Hwan, Jeong, Deog-Kyoon

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  7. 7
    A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

    A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector by Chi, Han-Kyu, Hwang, Moon-Sang, Yoo, Byoung-Joo, Choe, Won-Jun, Kim, Tae-Ho, Moon, Yong-Sam, Jeong, Deog-Kyoon

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  8. 8
    A Combined Clock and Data Recovery Circuit with Adaptive Cancellation of Data-Dependent Jitter

    A Combined Clock and Data Recovery Circuit with Adaptive Cancellation of Data-Dependent Jitter by Lee, Jin-Hee, Kim, Su-Hwan, Jeong, Deog-Kyoon

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