Search Results - AH LYAN LEE

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  1. 1
    A 553K-transistor LISP processor chip

    A 553K-transistor LISP processor chip by BOSSHART, P. W, HEWES, C. R, MAHANT-SHETTI, S. S, MATZKE, D. J, RUPAREL, K. N, SEXTON, J. F, CHING-HAO SHAW, SRIDHAR, T, STARK, D, AH LYAN LEE, ALES, M. D, MI-CHANG CHANG, KWOK KIT CHAU, FASHAM, K, HOAC, C. C, HOUSTON, T. W, VIBHU KALYAN, LUSKY, S. L

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  2. 2
    A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels

    A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels by PAYNE, Robert, LANDMAN, Paul, YIQUN XIE, PARTHASARATHY, Bharadwaj, BROUSE, Keith, MOHAMMED, Wahed, HERAGU, Keerthi, GUPTA, Vikas, DYSON, Lisa, LEE, Wai, BHAKTA, Bhavesh, RAMASWAMY, Sridhar, SONG WU, POWERS, John D, ULVI ERDOGAN, M, YEE, Ah-Lyan, GU, Richard, LIN WU

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  3. 3
    A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

    A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications by Payne, R., Bhakta, B., Ramaswamy, S., Song Wu, Powers, J., Landman, P., Erdogan, U., Ah-Lyan Yee, Gu, R., Lin Wu, Yiqun Xie, Parthasarathy, B., Brouse, K., Mohammed, W., Heragu, K., Gupta, V., Dyson, L., Wai Lee

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  4. 4
    A 62 Gb/s backplane interconnect ASIC based on 3.1 Gb/s serial-link technology

    A 62 Gb/s backplane interconnect ASIC based on 3.1 Gb/s serial-link technology by Landman, Paul, Yee, Ah-Lyan, Gu, Richard, Parthasarathy, Bharadwaj, Gupta, Vikas, Ramaswamy, Sridhar, Dyson, Lisa, Bosshart, Pat, Reynolds, Jeffrey, Frannhagen, Mats, Fremrot, Per, Johansson, Stefan, Lewis, Keith, Lee, Wai

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  5. 5
    A 6.25GHz 1V LC-PLL in 0.13/spl mu/m CMOS

    A 6.25GHz 1V LC-PLL in 0.13/spl mu/m CMOS by Richard Gu, Ah-Lyan Yee, Yiqun Xie, Wai Lee

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  6. 6
    A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications

    A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications by Landman, P., Brouse, K., Gupta, V., Song Wu, Payne, R., Erdogan, U., Gu, R., Ah-Lyan Yee, Parthasarathy, B., Ramaswamy, S., Bhakta, B., Mohammed, W., Powers, J., Yiqun Xie, Lin Wu, Dyson, L., Heragu, K., Wai Lee

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  7. 7
    A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology

    A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology by Landman, P., Ah-Lyan Yee, Gu, R., Parthasarathy, B., Gupta, V., Ramaswamy, S., Dyson, L., Bosshart, P., Reynolds, J., Frannhagen, M., Fremrot, P., Johansson, S., Lewis, K., Lee, W.

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  8. 8
    A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology

    A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology by Landman, P., Ah-Lyan Yee, Gu, R., Parthasarathy, B., Gupta, V., Ramaswamy, S., Dyson, L., Bosshart, P., Reynolds, J., Frannhagen, M., Fremrot, P., Johansson, S., Lewis, K., Wai Lee

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