Search Results - Aamodt, Tor M.

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  1. 1
    Reuse Distance-Based Probabilistic Cache Replacement

    Reuse Distance-Based Probabilistic Cache Replacement by Das, Subhasis, Aamodt, Tor M., Dally, William J.

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  2. 2
    Energy Efficient On-Demand Dynamic Branch Prediction Models

    Energy Efficient On-Demand Dynamic Branch Prediction Models by Mohammadi, Milad, Han, Song, Atoofian, Ehsan, Baniasadi, Amirali, Aamodt, Tor M., Dally, William J.

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  3. 3
    ReSprop: Reuse Sparsified Backpropagation

    ReSprop: Reuse Sparsified Backpropagation by Goli, Negar, Aamodt, Tor M.

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  4. 4
    Inter-Core Locality Aware Memory Scheduling

    Inter-Core Locality Aware Memory Scheduling by Dongdong Li, Aamodt, Tor M.

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  5. 5
    SLIP: Reducing wire energy in the memory hierarchy

    SLIP: Reducing wire energy in the memory hierarchy by Das, Subhasis, Aamodt, Tor M., Dally, William J.

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  6. 6
    Cache Coherence for GPU Architectures

    Cache Coherence for GPU Architectures by Singh, Inderpreet, Shriraman, Arrvindh, Fung, Wilson W.L., O'Connor, Mike, Aamodt, Tor M.

    Published in IEEE MICRO
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  7. 7
    Cache-Conscious Thread Scheduling for Massively Multithreaded Processors

    Cache-Conscious Thread Scheduling for Massively Multithreaded Processors by Rogers, T. G., O'Connor, M., Aamodt, T. M.

    Published in IEEE MICRO
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  8. 8
    Kilo TM: Hardware Transactional Memory for GPU Architectures

    Kilo TM: Hardware Transactional Memory for GPU Architectures by Fung, W. W. L., Singh, I., Brownsword, A., Aamodt, T.

    Published in IEEE MICRO
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  9. 9
    Cache-Conscious Wavefront Scheduling

    Cache-Conscious Wavefront Scheduling by Rogers, Timothy G., O'Connor, Mike, Aamodt, Tor M.

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  10. 10
    Formal-Analysis-Based Trace Computation for Post-Silicon Debug

    Formal-Analysis-Based Trace Computation for Post-Silicon Debug by Gort, M., De Paula, F. M., Kuan, J. J. W., Aamodt, T. M., Hu, A. J., Wilton, S. J. E., Jin Yang

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  11. 11
    Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs

    Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs by Chen, Xi E., Aamodt, Tor M.

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  12. 12
    Warp Scheduling for Fine-Grained Synchronization

    Warp Scheduling for Fine-Grained Synchronization by ElTantawy, Ahmed, Aamodt, Tor M.

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  13. 13
    Characterizing and Improving Resilience of Accelerators to Memory Errors in Autonomous Robots

    Characterizing and Improving Resilience of Accelerators to Memory Errors in Autonomous Robots by Shah, Deval, Xue, Zi Yu, Pattabiraman, Karthik, Aamodt, Tor M.

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  14. 14
    Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy

    Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy by Aamodt, Tor M., Chow, Paul

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  15. 15
    Emerald: Graphics Modeling for SoC Systems

    Emerald: Graphics Modeling for SoC Systems by Gubran, Ayub A., Aamodt, Tor M.

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  16. 16
    Throughput-Effective On-Chip Networks for Manycore Accelerators

    Throughput-Effective On-Chip Networks for Manycore Accelerators by Bakhoda, A, Kim, J, Aamodt, T M

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  17. 17
    Thread block compaction for efficient SIMT control flow

    Thread block compaction for efficient SIMT control flow by Fung, W W L, Aamodt, T M

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  18. 18
    Modeling Cache Contention and Throughput of Multiprogrammed Manycore Processors

    Modeling Cache Contention and Throughput of Multiprogrammed Manycore Processors by Chen, X. E., Aamodt, T.

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  19. 19
    Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow

    Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow by Fung, W.W.L., Sham, I., Yuan, G., Aamodt, T.M.

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  20. 20
    Cache coherence for GPU architectures

    Cache coherence for GPU architectures by Singh, I., Shriraman, A., Fung, W. W. L., O'Connor, M., Aamodt, T. M.

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