Search Results - Ababei, C.

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  1. 1
    Three-dimensional place and route for FPGAs

    Three-dimensional place and route for FPGAs by Ababei, C., Mogal, H., Bazargan, K.

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  2. 2
    STUDY REGARDING THE DEVELOPMENT OF LEG STRENGTH IN FIFTH GRADERS THROUGH PLYOMETRICS

    STUDY REGARDING THE DEVELOPMENT OF LEG STRENGTH IN FIFTH GRADERS THROUGH PLYOMETRICS by ABABEI, C, LĂSCUŞ, O.M.

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  3. 3
    Timing-driven partitioning-based placement for island style FPGAs

    Timing-driven partitioning-based placement for island style FPGAs by Maidee, P., Ababei, C., Bazargan, K.

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  4. 4
    Efficient Network Reconfiguration Using Minimum Cost Maximum Flow-Based Branch Exchanges and Random Walks-Based Loss Estimations

    Efficient Network Reconfiguration Using Minimum Cost Maximum Flow-Based Branch Exchanges and Random Walks-Based Loss Estimations by Ababei, C, Kavasseri, R

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  5. 5
    Camelina sativa Methanolic and Ethanolic Extract Potential in Alleviating Oxidative Stress, Memory Deficits, and Affective Impairments in Stress Exposure-Based Irritable Bowel Syndrome Mouse Models

    Camelina sativa Methanolic and Ethanolic Extract Potential in Alleviating Oxidative Stress, Memory Deficits, and Affective Impairments in Stress Exposure-Based Irritable Bowel Synd... by Copolovici, Dana M., Jurcoane, Stefana, Copolovici, Lucian, Copaci, Simona, Ciobica, Alin, Ababei, Daniela C., Hritcu, Luminita, Lefter, Radu, Balmus, Ioana-Miruna, Cojocariu, Roxana O., Mot, Silvia E. L.

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  6. 6
    Central and Peripheral Effect of MPTP Via Dose-Dependent Magnesium Modulation

    Central and Peripheral Effect of MPTP Via Dose-Dependent Magnesium Modulation by Lefter, R

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  7. 7
    Statistical Analysis and Design of HARP FPGAs

    Statistical Analysis and Design of HARP FPGAs by Gang Wang, Sivaswamy, S., Ababei, C., Bazargan, K., Kastner, R., Bozorgzadeh, E.

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  8. 8
    Determination of the Minimum Breakpoint Set of Directional Relay Networks Based on k-Trees of the Network Graphs

    Determination of the Minimum Breakpoint Set of Directional Relay Networks Based on k-Trees of the Network Graphs by Vinnakota, B.-R V., Ababei, C.

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  9. 9
    Timing minimization by statistical timing hMetis-based partitioning

    Timing minimization by statistical timing hMetis-based partitioning by Ababei, C., Bazargan, K.

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  10. 10
    Statistical timing driven partitioning for VLSI circuits

    Statistical timing driven partitioning for VLSI circuits by Ababei, C., Bazargan, K.

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  11. 11
    Placement and routing in 3D integrated circuits

    Placement and routing in 3D integrated circuits by Ababei, C., Feng, Y., Goplen, B., Hushrav Mogal, Zhang, T., Bazargan, K., Sachin Sapatnekar

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  12. 12
    Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis

    Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis by Ababei, C

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  13. 13
    Multi-objective circuit partitioning for cutsize and path-based delay minimization

    Multi-objective circuit partitioning for cutsize and path-based delay minimization by Ababei, C., Navaratnasothie, S., Bazargan, K., Karypis, G.

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  14. 14
    Energy and reliability oriented mapping for regular Networks-on-Chip

    Energy and reliability oriented mapping for regular Networks-on-Chip by Ababei, Cristinel, Kia, Hamed Sajjadi, Yadav, Om Prakash, Hu, Jingcao

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  15. 15
    Unified system level reliability evaluation methodology for multiprocessor Systems-on-Chip

    Unified system level reliability evaluation methodology for multiprocessor Systems-on-Chip by Yamamoto, A. Y., Ababei, C.

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  16. 16
    Efficient high-speed current-mode links for network-on-chip performance optimization

    Efficient high-speed current-mode links for network-on-chip performance optimization by Kia, H. S., Ababei, C.

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  17. 17
    Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration

    Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration by Kia, H. S., Ababei, C.

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  18. 18
    Achieving network on chip fault tolerance by adaptive remapping

    Achieving network on chip fault tolerance by adaptive remapping by Ababei, C., Katti, R.

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  19. 19
    Probabilistic aspects of crosstalk problems in CMOS ICs

    Probabilistic aspects of crosstalk problems in CMOS ICs by Ababei, C., Marculescu, R., Sundarajan, V.

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  20. 20
    Non-contiguous linear placement for reconfigurable fabrics

    Non-contiguous linear placement for reconfigurable fabrics by Ababei, C., Bazargan, K.

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