Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor by Afifah Maheran, A H, Menon, P S, Ahmad, I, Shaari, S, Elgomati, H A, Salehuddin, F

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Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method by Afifah Maheran, A H, Firhat, E N, Salehuddin, F, Mohd Zain, A S, Ahmad, I, Noor Faizah, Z A, Menon, P S, Elgomati, H A, Roslan, Ameer F

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Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor by AFIFAH MAHERAN, A. H, MENON, P. S, AHMAD, I, SHAARI, S

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Development of process parameters for 22 nm PMOS using 2-D analytical modeling by Maheran, A. H. Afifah, Menon, P. S., Shaari, S., Ahmad, I., Faizah, Z. A. Noor

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Optimization of 22nm Bi-GFET device for threshold voltage using Taguchi method by Izwanizam, Y., Maheran, A. H. Afifah, Salehuddin, F., Kaharudin, K. E.

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Threshold voltage optimization in a 22nm High-k/Salicide PMOS device by Maheran, A. H. Afifah, Menon, P. S., Ahmad, I., Yusoff, Z.

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Virtual fabrication in modelling 14 nm horizontal double gate bilayer graphene FET NMOS/PMOS by Nur Hazwani Naili, M. N., Afifah Maheran, A. H., Salehuddin, F., Kaharudin, K. E., Faizah, Z. A Noor

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Scaling down of the 32 nm to 22 nm gate length NMOS transistor by Afifah Maheran, A. H., Menon, P. S., Ahmad, I., Elgomati, H. A., Majlis, B. Y., Salehuddin, F.

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Beyond Nernst Sensitivity of Ion Sensitive Field Effect Transistor based on Ultra-Thin Body Box FDSOI by Zain, A S M, Dinar, Ahmed M., Salehuddin, F, Hazura, H, Hanim, A R, Idris, S K, Hamid, Afifah Maheran A

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Optimization of process parameter variations for 16nm DG-FinFET using Response Surface Methodology-Central Composite Design by Roslan, Ameer F, Salehuddin, F, Zain, A S M, Kaharudin, K E, Ahmad, I, Hazura, H, Hanim, A R, Idris, S K, Hamid, Afifah Maheran A

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Optimization of 10nm Bi-GFET Device for higher ION/IOFF ratio using Taguchi Method by Roslan, Ameer F, Kaharudin, K E, Salehuddin, F, Zain, A S M, Ahmad, I, Faizah, Z A N, Hazura, H, Hanim, A R, Idris, S K, Zaiton, A M, Mohamad, N R, Hamid, Afifah Maheran A

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Comparative Analysis of Process Parameter Variations in DGFinFET Device Using Statistical Methods by Roslan, Ameer F, Salehuddin, F, M Zain, A S, Mansor, Norhisham, Kaharudin, K E, Ahmad, I, Hazura, H, Hanim, A R, Idris, S K, Zaiton, A M, Zarina, B Z, Mohamad, N R, A Hamid, Afifah Maheran

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Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array by Salehuddin, F., Ahmad, I., Hamid, F. A., Zaharim, A., Hamid, A. M. A., Menon, P. S., Elgomati, H. A., Majlis, B. Y., Apte, P. R.

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