Bipolar transistor selected P-channel flash memory cell technology by Ohnakado, T., Ajika, N., Satoh, S.

Get full text

Influence of holes on neutral trap generation by Sakakibara, K., Ajika, N., Miyoshi, H.

Get full text

Device characteristics of 0.35 μm P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming by Ohnakado, T., Onoda, H., Sakamoto, O., Hayashi, K., Nishioka, N., Takada, H., Sugahara, K., Ajika, N., Satoh, S.

Get full text

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications by Nozoe, A., Kotani, H., Tsujikawa, T., Yoshida, K., Furusawa, K., Kato, M., Nishimoto, T., Kume, H., Kurata, H., Miyamoto, N., Kubono, S., Kanamitsu, M., Koda, K., Nakayama, T., Kouro, Y., Hosogane, A., Ajika, N., Koyashi, K.

Get full text

On a universal parameter of intrinsic oxide breakdown based on analysis of trap-generation characteristics by Sakakibara, K., Ajika, N., Miyoshi, H.

Get full text

Detailed observation of small leak current in flash memories with thin tunnel oxides by Manabe, Y., Okuyama, K., Kubota, K., Nozoe, A., Karashima, T., Ujiie, K., Kanno, H., Nakashima, M., Ajika, N.

Get full text

Identification of stress-induced leakage current components and the corresponding trap models in SiO/sub 2/ films by Sakakibara, K., Ajika, N., Hatanaka, M., Miyoshi, H., Yasuoka, A.

Get full text

A quantitative analysis of time-decay reproducible stress-induced leakage current in SiO/sub 2/ films by Sakakibara, K., Ajika, N., Eikyu, K., Ishikawa, K., Miyoshi, H.

Get full text

A True 6F2 NOR Flash Memory Cell Technology - Impact of Floating Gate B4-Flash on NOR Scaling by Shimizu, S, Shukuri, S, Ajika, N, Ogura, T, Mihara, M, Kawajiri, Y, Kobayashi, K, Nakashima, M

Request full text

Highly Reliable B4-Flash Technology for High Density Embedded NVM Application by Ajika, N, Shukuri, S, Shimizu, S, Ogura, T, Mihara, M, Kobayashi, K, Nakashima, M

Request full text

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory by Kobayashi, S., Nakai, H., Kunori, Y., Nakayama, T., Miyawaki, Y., Terada, Y., Onoda, H., Ajika, N., Hatanaka, M., Miyoshi, H., Yoshihara, T.

Get full text

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories by Miyawaki, Y., Nakayama, T., Kobayashi, S., Ajika, N., Ohi, M., Terada, Y., Arima, H., Yoshihara, T.

Get full text

High programming throughput 0.35 mu m p-channel DINOR flash memory by Sakamoto, O, Onoda, H, Katayama, T, Hayashi, K, Yamasaki, N, Sakakibara, K, Ohnakado, T, Takada, H, Tsuji, N, Ajika, N, Hatanaka, M, Miyoshi, H

Get full text

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller by Nakayama, T., Kobayashi, S., Miyawaki, Y., Terada, Y., Ajika, N., Ohi, M., Arima, H., Matsukawa, T., Yoshihara, T., Suzuki, K.

Get full text

A 60nm NOR Flash Memory Cell Technology Utilizing Back Bias Assisted Band-to-Band Tunneling Induced Hot-Electron Injection (B4-Flash) by Shukuri, S., Ajika, N., Mihara, M., Kobayashi, K., Endoh, T., Nakashima, M.

Request full text

120-ns 128 K8-bit/64 K16-bit CMOS EEPROMs by Terada, Y., Kobayashi, K., Nakayama, T., Hayashikoshi, M., Miyawaki, Y., Ajika, N., Arima, H., Matsukawa, T., Yoshihara, T.

Get full text

A 10k-Cycling Reliable 90nm Logic NVM "eCFlash" (Embedded CMOS Flash) Technology by Shukuri, S, Shimizu, S, Ajika, N, Ogura, T, Mihara, M, Kawajiri, Y, Kobayashi, K, Nakashima, M

Request full text

Construction of an energy filter for 200 kV CTEM by Oikawa, T., Ajika, N., Hashimoto, H., Kokubo, Y., Yamaguchi, K.

Get full text

Identification of stress-induced leakage current components and thecorresponding trap models in SiO(2) films MOStransistors by Sakakibara, K, Ajika, N, Hatanaka, M, Miyoshi, H, Yasuoka, A

Get full text

Identification of stress-induced leakage current components and the corresponding trap models in SiO/sub 2/ films [MOS transistors] by Sakakibara, K., Ajika, N., Hatanaka, M., Miyoshi, H., Yasuoka, A.

Get full text