Search Results - Akashe, S.

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  1. 1
    FinFET Based Tunable Analog Circuit : Design and Analysis at 45 nm Technology

    FinFET Based Tunable Analog Circuit : Design and Analysis at 45 nm Technology by Kushwah, Ravindra Singh, Akashe, Shyam

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  2. 2
    Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

    Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell by Sikarwar, Vandna, Khandelwal, Saurabh, Akashe, Shyam

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  3. 3
    Reduction of leakage current and power in full subtractor using MTCMOS technique

    Reduction of leakage current and power in full subtractor using MTCMOS technique by Gautam, M., Akashe, S.

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  4. 4
    Designing and simulation of full adder cell using FINFET technique

    Designing and simulation of full adder cell using FINFET technique by Saraswat, R., Akashe, S., Babu, S.

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  5. 5
    Performance analysis of ultra deep sub micron and deep sub micron technology using complementary metal oxide semiconductor inverter

    Performance analysis of ultra deep sub micron and deep sub micron technology using complementary metal oxide semiconductor inverter by Soni, U., Akashe, S.

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  6. 6
    Analytical modeling and simulation of two dimensional double gate nanoscale SOI MOSFET

    Analytical modeling and simulation of two dimensional double gate nanoscale SOI MOSFET by Kushwah, R. S., Akashe, S.

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  7. 7
    A novel high-performance CMOS 1 bit full-adder cell

    A novel high-performance CMOS 1 bit full-adder cell by Dubey, A., Akashe, S., Dubey, S.

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  8. 8
    Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology

    Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology by Manorama, M., Shrivastava, P., Akashe, S.

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  9. 9
    Design and operating characteristics of voltage comparator using MTCMOS circuits

    Design and operating characteristics of voltage comparator using MTCMOS circuits by Mishra, S., Pandey, V., Akashe, S.

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  10. 10
    Design low power 10T full adder using process and circuit techniques

    Design low power 10T full adder using process and circuit techniques by Mishra, S., Tomar, S. S., Akashe, S.

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  11. 11
    Design of a FinFET based inverter using MTCMOS and SVL leakage reduction technique

    Design of a FinFET based inverter using MTCMOS and SVL leakage reduction technique by Manorama, Khandelwal, S., Akashe, S.

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  12. 12
    Transistor gating: Reduction of leakage current and power in full subtractor circuit

    Transistor gating: Reduction of leakage current and power in full subtractor circuit by Gautam, M., Akashe, S.

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  13. 13
    Comparative Analysis of Schmitt Trigger with AVL (AVLG and AVLS) Technique Using Nanoscale CMOS Technology

    Comparative Analysis of Schmitt Trigger with AVL (AVLG and AVLS) Technique Using Nanoscale CMOS Technology by Saxena, A., Akashe, S.

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  14. 14
    Design and analysis of tunable analog circuit using double gate MOSFET at 45nm CMOS technology

    Design and analysis of tunable analog circuit using double gate MOSFET at 45nm CMOS technology by Kushwah, R. S., Akashe, S.

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  15. 15
    A competent design of 2∶1 multiplexer and its application in 1-bit full adder cell

    A competent design of 2∶1 multiplexer and its application in 1-bit full adder cell by Dubey, Amit, Dubey, S., Akashe, S.

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  16. 16
    Modeling and simulation of low power 14 T full adder with reduced ground bounce noise at 45 nm technology

    Modeling and simulation of low power 14 T full adder with reduced ground bounce noise at 45 nm technology by Singh, R., Akashe, S.

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  17. 17
    Leakage Minimization of 10T Full Adder Using Deep Sub-micron Technique

    Leakage Minimization of 10T Full Adder Using Deep Sub-micron Technique by Mishra, S., Akashe, S.

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  18. 18
    Low power analysis in single stage source coupled VCO with AVL technique using nanoscale CMOS technology

    Low power analysis in single stage source coupled VCO with AVL technique using nanoscale CMOS technology by Shrivastava, A., Khandelwal, S., Akashe, S.

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  19. 19
    Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET

    Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET by Sikarwar, V., Khandelwal, S., Akashe, S.

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  20. 20
    Analysis of power in 3T DRAM and 4T DRAM Cell design for different technology

    Analysis of power in 3T DRAM and 4T DRAM Cell design for different technology by Akashe, S., Mudgal, A., Singh, S. B.

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