Search Results - AlMashary, B.

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  1. 1
    Stress-induced vertical confinement of light in bulk GaAs and Si substrates

    Stress-induced vertical confinement of light in bulk GaAs and Si substrates by Almashary, B.A., Hong Koo Kim

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  2. 2
    Current-mode triangular wave generator using CCIIs

    Current-mode triangular wave generator using CCIIs by Almashary, B, Alhokail, H

    Published in Microelectronics
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  3. 3
    Genetic algorithm based diode model prameters extraction

    Genetic algorithm based diode model prameters extraction by Almashary, B.

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  4. 4
    Estimation of band-gap offsets of heterojunctions using J-V-T characteristics

    Estimation of band-gap offsets of heterojunctions using J-V-T characteristics by Debbar, N., Almashary, B.

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  5. 5
    Simulation technique for noise and timing jitter in phase locked loop

    Simulation technique for noise and timing jitter in phase locked loop by Telba, A., Noras, J.M., Abou El Ela, M., Almashary, B.

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  6. 6
    A proposed FPGA-based parallel architecture for matrix multiplication

    A proposed FPGA-based parallel architecture for matrix multiplication by Qasim, S.M., Abbasi, S.A., Almashary, B.

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  7. 7
    An overview of advanced FPGA architectures for optimized hardware realization of computation intensive algorithms

    An overview of advanced FPGA architectures for optimized hardware realization of computation intensive algorithms by Qasim, S.M., Abbasi, S.A., Almashary, B.

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  8. 8
    A review of FPGA-based design methodology and optimization techniques for efficient hardware realization of computation intensive algorithms

    A review of FPGA-based design methodology and optimization techniques for efficient hardware realization of computation intensive algorithms by Qasim, S.M., Abbasi, S.A., Almashary, B.

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  9. 9
    Behavioural Modelling and Simulation of Dual Cascaded PLL Based Frequency Synthesizer

    Behavioural Modelling and Simulation of Dual Cascaded PLL Based Frequency Synthesizer by Telba, A.A., Qasim, S.M., Noras, J.M., Almashary, B., El Ela, M.A.

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  10. 10
    Jitter minimization in Digital Transmission using dual phase locked loops

    Jitter minimization in Digital Transmission using dual phase locked loops by Telba, A., Noras, J.M., Abou El Ela, M., AlMashary, B.

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