Search Results - Albonesi, D.H.

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  1. 1
    Selective cache ways: on-demand cache resource allocation

    Selective cache ways: on-demand cache resource allocation by Albonesi, D.H.

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  2. 2
    Reducing the complexity of the register file in dynamic superscalar processors

    Reducing the complexity of the register file in dynamic superscalar processors by Balasubramonian, R., Dwarkadas, S., Albonesi, D.H.

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  3. 3
    On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions

    On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions by Haurylau, M., Guoqing Chen, Hui Chen, Jidong Zhang, Nelson, N.A., Albonesi, D.H., Friedman, E.G., Fauchet, P.M.

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  4. 4
    A dynamically tunable memory hierarchy

    A dynamically tunable memory hierarchy by Balasubramonian, R., Albonesi, D.H., Buyuktosunoglu, A., Dwarkadas, S.

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  5. 5
    Dynamic frequency and voltage control for a multiple clock domain microarchitecture

    Dynamic frequency and voltage control for a multiple clock domain microarchitecture by Semeraro, G., Albonesi, D.H., Dropsho, S.G., Magklis, G., Dwarkadas, S., Scott, M.L.

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  6. 6
    Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

    Leveraging Optical Technology in Future Bus-based Chip Multiprocessors by Kirman, Nevin, Kirman, Meyrem, Dokania, Rajeev K., Martinez, Jose F., Apsel, Alyssa B., Watkins, Matthew A., Albonesi, David H.

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  7. 7
    Dynamically tuning processor resources with adaptive processing

    Dynamically tuning processor resources with adaptive processing by Albonesi, D. H., Balasubramonian, R., Dropsbo, S. G., Dwarkadas, S., Friedman, E. G., Huang, M. C., Kursun, V., Magklis, G., Scott, M. L., Semeraro, G., Bose, P., Buyuktosunoglu, A., Cook, P. W., Schuster, S. E.

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  8. 8
    Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences

    Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences by Albonesi, D.H.

    Published in IEEE MICRO
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  9. 9
    Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor

    Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor by Magklis, G., Semeraro, G., Albonesi, D.H., Dropsho, S.G., Dwarkadas, S., Scott, M.L.

    Published in IEEE MICRO
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  10. 10
    Scheduling algorithms for unpredictably heterogeneous CMP architectures

    Scheduling algorithms for unpredictably heterogeneous CMP architectures by Winter, J.A., Albonesi, D.H.

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  11. 11
    Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

    Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling by Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Scott, M.L.

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  12. 12
    Front-end policies for improved issue efficiency in SMT processors

    Front-end policies for improved issue efficiency in SMT processors by El-Moursy, A., Albonesi, D.H.

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  13. 13
    Localized microarchitecture-level voltage management

    Localized microarchitecture-level voltage management by YongKang Zhu, Albonesi, D.H.

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  14. 14
    Power-efficient error tolerance in chip multiprocessors

    Power-efficient error tolerance in chip multiprocessors by Rashid, M.W., Tan, E.J., Huang, M.C., Albonesi, D.H.

    Published in IEEE MICRO
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  15. 15
    On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions

    On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions by Guoqing Chen, Hui Chen, Haurylau, M., Nelson, N.A., Albonesi, D.H., Fauchet, P.M., Friedman, E.G.

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  16. 16
    Guest editors' introduction: Power and complexity aware design

    Guest editors' introduction: Power and complexity aware design by Bose, P., Albonesi, D.H., Marculescu, D.

    Published in IEEE MICRO
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  17. 17
    Integrating adaptive on-chip storage structures for reduced dynamic power

    Integrating adaptive on-chip storage structures for reduced dynamic power by Dropsho, S., Buyuktosunoglu, A., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Semeraro, G., Magklis, G., Scottt, M.L.

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  18. 18
    Managing static leakage energy in microprocessor functional units

    Managing static leakage energy in microprocessor functional units by Dropsho, S., Kursun, V., Albonesi, D.H., Dwarkadas, S., Friedman, E.G.

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  19. 19
    Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

    Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor by Magklis, G., Scott, M.L., Semeraro, G., Albonesi, D.H., Dropsho, S.

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  20. 20
    Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors

    Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors by Lopez, S., Dropsho, S., Albonesi, D.H., Garnica, O., Lanchares, J.

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