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Profile and Etch Characterization of High Wafer Temperature Etched Y1/Pt Stacks
by
MARKS, S.
,
ALMERICO, J. P.
Published in
Integrated ferroelectrics
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The Profile and Device Characterization of High Wafer Temperature Etched Ir/PZT/Ir Stacks
by
Marks, S.
,
Almerico, J. P.
,
Gay, M. K.
,
Celii, F. G.
Published in
Integrated ferroelectrics
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Contamination issues in plasma etching of non-volatile materials: managing by-product deposition
by
Olson, K.A.
,
Jerde, L.
,
Almerico, J.P.
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Feasibility analysis for dry plasma scribe lane etch for die separation in compound semiconductors
by
Almerico, J.P.
,
Werbaneth, P.F.
,
Cho, Y.K.
Published in
III-Vs review
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Pt/PZT/Pt and Pt/barrier stack etches for MEMS devices in a dual frequency high density plasma reactor
by
Werbaneth, P.
,
Almerico, J.
,
Jerde, L.
,
Marks, S.
,
Wachtmann, B.
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