Search Results - Amaricai, A.

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  1. 1
    Check node unit for LDPC decoders based on one-hot data representation of messages

    Check node unit for LDPC decoders based on one-hot data representation of messages by Boncalo, O, Amaricai, A, Savin, V, Declercq, D, Ghaffari, F

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  2. 2
    Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions

    Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions by NIMARA, S., AMARICAI, A., BONCALO, O., POPA, M.

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  3. 3
    Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits

    Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits by Boncalo, O., Udrescu, M., Prodan, L., Vladutiu, M., Amaricai, A.

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  4. 4
    Analysis of transient error propagation in sub-powered CMOS circuits

    Analysis of transient error propagation in sub-powered CMOS circuits by Nimara, S., Amaricai, A., Popa, M.

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  5. 5
    Logical fault modeling of source drain short defects for CMOS reversible circuits

    Logical fault modeling of source drain short defects for CMOS reversible circuits by Boncalo, O, Amaricai, A

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  6. 6
    FPGA implementation of very high radix square root with prescaling

    FPGA implementation of very high radix square root with prescaling by Amaricai, A., Boncalo, O.

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  7. 7
    Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation

    Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation by Boncalo, O., Amaricai, A.

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  8. 8
    Performance evaluation of faulty iterative decoders using absorbing Markov chains

    Performance evaluation of faulty iterative decoders using absorbing Markov chains by Ivanis, Predrag, Vasic, Bane, Declercq, David

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  9. 9
    A moving window architecture for a HW/SW codesign based Canny edge detection for FPGA

    A moving window architecture for a HW/SW codesign based Canny edge detection for FPGA by Amaricai, A., Boncalo, O., Iordate, M., Marinescu, B.

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  10. 10
    Accuracy analysis of the parallel composition for the block diagram based reliability assessment of quantum circuits

    Accuracy analysis of the parallel composition for the block diagram based reliability assessment of quantum circuits by Boncalo, O, Vladutiu, M, Amaricai, A

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  11. 11
    Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation

    Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation by Amaricai, A., Boncalo, O.

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  12. 12
    Two phase simulation-based assessment of quantum error correction codes

    Two phase simulation-based assessment of quantum error correction codes by Boncalo, O., Vladutiu, M., Amaricai, A.

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  13. 13
    Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator

    Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator by Amaricai, A, Dobre, A, Boncalo, O, Tanase, A, Valuch, C

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  14. 14
    Design of floating point units for interval arithmetic

    Design of floating point units for interval arithmetic by Amaricai, A., Vladutiu, M., Boncalo, O.

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  15. 15
    Hardware Support for Combined Interval and Floating Point Multiplication

    Hardware Support for Combined Interval and Floating Point Multiplication by Amaricai, A., Vladutiu, M., Prodan, L., Udrescu, M., Boncalo, O.

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  16. 16
    A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units

    A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units by Petcu, V.E., Amaricai, A., Vladutiu, M.

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  17. 17
    Floating point multiplication rounding schemes for interval arithmetic

    Floating point multiplication rounding schemes for interval arithmetic by Amaricai, A., Vladutiu, M., Udrescu, M., Prodan, L., Boncalo, O.

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  18. 18
    Assessing quantum circuits reliability with mutant-based simulated fault injection

    Assessing quantum circuits reliability with mutant-based simulated fault injection by Boncalo, O., Udrescu, M., Prodan, L., Vladutiu, M., Amaricai, A.

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  19. 19
    Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor

    Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor by Amaricai, A., Vladutiu, M., Prodan, L., Udrescu, M., Boncalo, O.

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  20. 20
    Error-Model Driven Analysis of Quantum Circuits Reliability

    Error-Model Driven Analysis of Quantum Circuits Reliability by Boncalo, O., Udrescu, M., Prodan, L., Vladutiu, M., Amaricai, A.

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