Search Results - Amaricai, Alexandru

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  1. 1
    Probability density function modeling for sub-powered interconnects

    Probability density function modeling for sub-powered interconnects by Pater, Flavius, Amaricăi, Alexandru

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  2. 2
    Design Trade-offs in Configurable FPGA Architectures for K-Means Clustering

    Design Trade-offs in Configurable FPGA Architectures for K-Means Clustering by AMARICAI, Alexandru

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  3. 3
    Low-precision DSP-based floating-point multiply-add fused for Field Programmable Gate Arrays

    Low-precision DSP-based floating-point multiply-add fused for Field Programmable Gate Arrays by Amaricai, Alexandru, Boncalo, Oana, Gavriliu, Constantina-Elena

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  4. 4
    Quantum circuit’s reliability assessment with VHDL-based simulated fault injection

    Quantum circuit’s reliability assessment with VHDL-based simulated fault injection by Boncalo, Oana, Amăricăi, Alexandru, Udrescu, Mihai, Vlăduţiu, Mircea

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  5. 5
    Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation

    Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation by Boncalo, Oana, Kolumban-Antal, Gyorgy, Amaricai, Alexandru, Savin, Valentin, Declercq, David

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  6. 6
    Fault Tolerant Digital Data-Path Design via Control Feedback Loops

    Fault Tolerant Digital Data-Path Design via Control Feedback Loops by Boncalo, Oana, Amaricai, Alexandru, Lendek, Zsófia

    Published in Electronics (Basel)
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  7. 7
    Memory trade-offs in layered self-corrected min-sum LDPC decoders

    Memory trade-offs in layered self-corrected min-sum LDPC decoders by Boncalo, Oana, Amaricai, Alexandru, Mihancea, Petru Florin, Savin, Valentin

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  8. 8
    Design Issues and Implementations for Floating-Point Divide-Add Fused

    Design Issues and Implementations for Floating-Point Divide-Add Fused by Amaricai, Alexandru, Vladutiu, Mircea, Boncalo, Oana

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  9. 9
    Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits

    Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits by Boncalo, O., Udrescu, M., Prodan, L., Vladutiu, M., Amaricai, A.

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  10. 10
    Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions

    Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions by NIMARA, S., AMARICAI, A., BONCALO, O., POPA, M.

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  11. 11
    Iterative Gradient Descent Decoding for Real Number LDPC Codes

    Iterative Gradient Descent Decoding for Real Number LDPC Codes by Boncalo, Oana, Amaricai, Alexandru

    Published in arXiv.org
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  12. 12
    Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders

    Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders by Boncalo, Oana, Amaricai, Alexandru

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  13. 13
    Assessing quantum circuits reliability with mutant-based simulated fault injection

    Assessing quantum circuits reliability with mutant-based simulated fault injection by Boncalo, O., Udrescu, M., Prodan, L., Vladutiu, M., Amaricai, A.

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  14. 14
    Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor

    Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor by Amaricai, A., Vladutiu, M., Prodan, L., Udrescu, M., Boncalo, O.

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  15. 15
    Simulated Fault Injection for Quantum Circuits Based on Simulator Commands

    Simulated Fault Injection for Quantum Circuits Based on Simulator Commands by Boncalo, O., Udrescu, M., Prodan, L., Vladutiu, M., Amaricai, A.

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  16. 16
    Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing

    Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing by Boncalo, Oana, Amaricai, Alexandru, Hera, Andrei, Savin, Valentin

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  17. 17
    Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

    Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits by Jiaoyan Chen, Spagnol, Christian, Grandhi, Satish, Popovici, Emanuel, Cotofana, Sorin, Amaricai, Alexandru

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  18. 18
    FPGA implementation of very high radix square root with prescaling

    FPGA implementation of very high radix square root with prescaling by Amaricai, A., Boncalo, O.

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  19. 19
    An FPGA sliding window-based architecture harris corner detector

    An FPGA sliding window-based architecture harris corner detector by Amaricai, Alexandru, Gavriliu, Constantina-Elena, Boncalo, Oana

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  20. 20
    FPGA implementation of hybrid fixed point - Floating point multiplication

    FPGA implementation of hybrid fixed point - Floating point multiplication by Amaricai, Alexandru, Boncalo, Oana, Sicoe, Ovidiu, Marcu, Marius

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