On the study of p-channel thin-film transistors fabricated by SLS ELA crystallization techniques by Exarchos, M.A., Moschou, D.C., Papaioannou, G.J., Kouvatsos, D.N., Arapoyanni, A., Voutsas, A.T.

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A Design Technique for Energy Reduction in NORA CMOS Logic by Limniotis, K., Tsiatouhas, Y., Haniotakis, T., Arapoyanni, A.

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A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs by Matakias, S, Tsiatouhas, Y, Arapoyanni, A, Haniotakis, Th

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A Built-In Voltage Measurement Technique for the Calibration of RF Mixers by Liaperdos, J., Arapoyanni, A., Tsiatouhas, Y.

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Reliability and defectivity comparison of n- and p-channel SLS ELA polysilicon TFTs fabricated with a novel crystallization technique by Moschou, D.C., Exarchos, M.A., Kouvatsos, D.N., Papaioannou, G.J., Arapoyanni, A., Voutsas, A.T.

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Charge Pump Circuits for Low-voltage Applications by Moisiadis, Y., Bouras, I., Arapoyanni, A.

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A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators by Dermentzoglou, L, Tsiatouhas, Y, Arapoyanni, A

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A high-density DRAM cell with built-in gain stage by Kamoulakos, G., Tsiatouhas, Y., Chrisanthopoulos, A., Arapoyanni, A.

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Management of charge pump circuits by Kamoulakos, G., Chrisanthopoulos, A., Tsiatouhas, Y., Arapoyanni, A.

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A Current Mode, Parallel, Two-Rail Code Checker by Matakias, Sotirios, Tsiatouhas, Yiorgos, Haniotakis, Themistoklis, Arapoyanni, Angela

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Single event upset tolerance in flip-flop based microprocessor cores by Valadimas, S., Tsiatouhas, Y., Arapoyanni, A., Evans, A.

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High fan-in differential current mirror logic by Tsiatouhas, Y., Arapoyanni, A.

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A design for testability technique for mixed-signal differential circuits by Dermentzoglou, L, Tsiatouhas, Y, Arapoyanni, A

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A built-in self-test scheme for differential ring oscillators by Dermentzoglou, L., Tsiatouhas, Y., Arapoyanni, A.

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A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs by Tsiatouhas, Y., Matakias, S., Arapoyanni, A., Haniotakis, Th

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Ultra fast and low cost parallel two-rail code checker targeting high fan-in applications by Matakias, S., Tsiatouhas, Y., Haniotakis, Th, Arapoyanni, A.

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Fast, parallel two-rail code checker with enhanced testability by Matakias, S., Arapoyanni, A., Efthymiou, A., Tsiatouhas, Y., Haniotakis, T.

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A hierarchical architecture for concurrent soft error detection based on current sensing by Tsiatouhas, Y., Arapoyanni, A., Nikolos, D., Haniotakis, T.

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Impact of the S/D extension doping profile on the psi -cell concept by Kamoulakos, G, McCarthy, D, Papadas, C, Arapoyanni, A

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A low power NORA circuit design technique based on charge recycling by Tsiatouhas, Y., Limniotis, K., Arapoyanni, A., Haniotakis, T.

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