Search Results - Arda, Samet E.

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  1. 1
    Performant, Multi-Objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices

    Performant, Multi-Objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices by Mack, Joshua, Arda, Samet E., Ogras, Umit Y., Akoglu, Ali

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  2. 2
    Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems

    Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems by Krishnakumar, Anish, Arda, Samet E., Goksoy, A. Alper, Mandal, Sumit K., Ogras, Umit Y., Sartor, Anderson L., Marculescu, Radu

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  3. 3
    Nonlinear dynamic modeling and simulation of a passively cooled small modular reactor

    Nonlinear dynamic modeling and simulation of a passively cooled small modular reactor by Arda, Samet E., Holbert, Keith E.

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  4. 4
    A dynamic model of a passively cooled small modular reactor for controller design purposes

    A dynamic model of a passively cooled small modular reactor for controller design purposes by Arda, Samet E., Holbert, Keith E.

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  5. 5
    HiLITE: Hi erarchical and L ightweight I mita t ion L e arning for Power Management of Embedded SoCs

    HiLITE: Hi erarchical and L ightweight I mita t ion L e arning for Power Management of Embedded SoCs by Sartor, Anderson L., Krishnakumar, Anish, Arda, Samet E., Ogras, Umit Y., Marculescu, Radu

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  6. 6
    DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework

    DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework by Arda, Samet E., Krishnakumar, Anish, Goksoy, A. Alper, Kumbhare, Nirmal, Mack, Joshua, Sartor, Anderson L., Akoglu, Ali, Marculescu, Radu, Ogras, Umit Y.

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  7. 7
    HiLITE: Hierarchical and Lightweight Imitation Learning for Power Management of Embedded SoCs

    HiLITE: Hierarchical and Lightweight Imitation Learning for Power Management of Embedded SoCs by Sartor, Anderson L., Krishnakumar, Anish, Arda, Samet E., Ogras, Umit Y., Marculescu, Radu

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  8. 8
    DS3: A System-Level D omain- S pecific S ystem-on-Chip S imulation Framework

    DS3: A System-Level D omain- S pecific S ystem-on-Chip S imulation Framework by Arda, Samet E, Krishnakumar, Anish, A Alper Goksoy, Kumbhare, Nirmal, Mack, Joshua, Sartor, Anderson L, Akoglu, Ali, Marculescu, Radu, Ogras, Umit Y

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  9. 9
    Performant, Multi-objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices

    Performant, Multi-objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices by Mack, Joshua, Arda, Samet E, Ogras, Umit Y, Akoglu, Ali

    Published in arXiv.org
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  10. 10
    Runtime Task Scheduling using Imitation Learning for Heterogeneous Many-Core Systems

    Runtime Task Scheduling using Imitation Learning for Heterogeneous Many-Core Systems by Krishnakumar, Anish, Arda, Samet E, A Alper Goksoy, Mandal, Sumit K, Ogras, Umit Y, Sartor, Anderson L, Marculescu, Radu

    Published in arXiv.org
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  11. 11
    DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework

    DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework by Arda, Samet E, Anish, N K, A Alper Goksoy, Kumbhare, Nirmal, Mack, Joshua, Sartor, Anderson L, Akoglu, Ali, Marculescu, Radu, Ogras, Umit Y

    Published in arXiv.org
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  12. 12
    Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips

    Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips by Arda, Samet E, Anish, N K, A Alper Goksoy, Mack, Joshua, Kumbhare, Nirmal, Sartor, Anderson L, Akoglu, Ali, Marculescu, Radu, Ogras, Umit Y

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