Latent interface-trap buildup and its implications for hardness assurance (MOS transistors) by Schwank, J.R., Fleetwood, D.M., Shaneyfelt, M.R., Winokur, P.S., Axness, C.L., Riewe, L.C.

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Modeling the time-dependent transient radiation response of semiconductor junctions by Wunsch, T.F., Axness, C.L.

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SEU simulation and testing of resistor-hardened D-latches in the SA3300 microprocessor by Sexton, F.W., Corbett, W.T., Treece, R.K., Hass, K.J., Hughes, K.L., Axness, C.L., Hash, G.L., Shaneyfelt, M.R., Wunsch, T.F.

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Radiation characteristics of SIPOS and polysilicon resistors by Axness, C.L., Riewe, L., Reber, R.A., Liang, A.Y., Ang, S.S., Brown, W.D.

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Memory SEU simulations using 2-D transport calculations by Fu, J.S., Axness, C.L., Weaver, H.T.

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SEU characterization and design dependence of the SA3300 microprocessor by Sexton, F.W., Treece, R.K., Hass, K.J., Hughes, K.L., Hash, G.L., Axness, C.L., Buchner, S.P., Kang, K.

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RAM cell recovery mechanisms following high-energy ion strikes by Weaver, H.T., Axness, C.L., Fu, J.S., Binkley, J.S., Mansfield, J.

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A proposed new structure for SEU immunity in SRAM employing drain resistance by Ochoa, A., Axness, C.L., Weaver, H.T., Fu, J.S.

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Single event upset in irradiated 16 K CMOS SRAMs by Axness, C.L., Schwank, J.R., Winokur, P.S., Browning, J.S., Koga, R., Fleetwood, D.M.

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Single Event Upset In CMOS Static Ram And Latches by Axness, C.L., Weaver, H.T., Giddings, A.E., Shafer, B.D.

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