Search Results - Bae, Geumjong

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  1. 1
    24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit

    24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit by Song, Taejoong, Rim, Woojin, Kim, Hoonki, Cho, Keun Hwi, Kim, Taeyeong, Lee, TaeJung, Bae, Geumjong, Kim, Dong-Won, Kwon, SD, Baek, Sanghoon, Jung, Jonghoon, Kye, Jongwook, Jung, Hakchul, Kim, Hyungtae, Jung, Soon-Moon, Park, Jaehong

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  2. 2
    Retention Mechanism of Localized Silicon–Oxide–Nitride–Oxide–Silicon Embedded NOR Device

    Retention Mechanism of Localized Silicon–Oxide–Nitride–Oxide–Silicon Embedded NOR Device by Hyun, JaeWoong, Jeong, YounSeok, Chae, HeeSoon, Seo, Sunae, Kim, JinHee, Um, MyungYoon, Lee, ByoungJin, Kim, KiChul, Cho, InWook, Bae, GeumJong, Lee, NaeIn, Kim, ChungWoo

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  3. 3
    3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

    3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications by Bae, Geumjong, Bae, D.-I., Kang, M., Hwang, S.M., Kim, S.S., Seo, B., Kwon, T.Y., Lee, T.J., Moon, C., Choi, Y.M., Oikawa, K., Masuoka, S., Chun, K.Y., Park, S.H., Shin, H.J., Kim, J.C., Bhuwalka, K.K., Kim, D.H., Kim, W.J., Yoo, J., Jeon, H.Y., Yang, M.S., Chung, S.-J., Kim, D., Ham, B.H., Park, K.J., Kim, W.D., Park, S.H., Song, G., Kim, Y.H., Kang, M.S., Hwang, K.H., Park, C.-H., Lee, J.-H., Kim, D.-W., Jung, S-M., Kang, H.K.

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  4. 4
    Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB

    Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB by Guangfan Jiao, Toledano-Luque, Maria, Kab-Jin Nam, Toshiro, Nakanishi, Seung-Hun Lee, Jin-Soak Kim, Kauerauf, Thomas, EunAe Chung, Dong-il Bae, Geumjong Bae, Dong-Won Kim, Kihyun Hwang

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  5. 5
    A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

    A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond by Bae, Dong-il, Bae, Geumjong, Bhuwalka, Krishna K, Lee, Seung-Hun, Song, Myung-Geun, Jeon, Taek-soo, Kim, Cheol, Kim, Wookje, Park, Jaeyoung, Kim, Sunjung, Kwon, Uihui, Jeon, Jongwook, Nam, Kab-Jin, Lee, Sangwoo, Lian, Sean, Seo, Kang-ill, Lee, Sun-Ghil, Jae Hoo Park, Heo, Yeon-Cheol, Rodder, Mark S., Kittl, Jorge A., Kim, Yihwan, Hwang, Kihyun, Kim, Dong-Won, Liang, Mong-song, Jung, E.S.

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