Search Results - Becker, Dale

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  1. 1
    Effectiveness of short sections of wildlife fencing and crossing structures along highways in reducing wildlife–vehicle collisions and providing safe crossing opportunities for large mammals

    Effectiveness of short sections of wildlife fencing and crossing structures along highways in reducing wildlife–vehicle collisions and providing safe crossing opportunities for lar... by Huijser, Marcel P., Fairbank, Elizabeth R., Camel-Means, Whisper, Graham, Jonathan, Watson, Vicki, Basting, Pat, Becker, Dale

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  2. 2
    A Hybrid Methodology for Jitter and Eye Estimation in High-Speed Serial Channels Using Polynomial Chaos Surrogate Models

    A Hybrid Methodology for Jitter and Eye Estimation in High-Speed Serial Channels Using Polynomial Chaos Surrogate Models by Ahadi Dolatsara, Majid, Hejase, Jose Ale, Becker, Wiren Dale, Swaminathan, Madhavan

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  3. 3
    Demystifying Machine Learning for Signal and Power Integrity Problems in Packaging

    Demystifying Machine Learning for Signal and Power Integrity Problems in Packaging by Swaminathan, Madhavan, Torun, Hakki Mert, Yu, Huan, Hejase, Jose Ale, Becker, Wiren Dale

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  4. 4
    Worst-Case Eye Analysis of High-Speed Channels Based on Bayesian Optimization

    Worst-Case Eye Analysis of High-Speed Channels Based on Bayesian Optimization by Dolatsara, Majid Ahadi, Hejase, Jose Ale, Becker, Wiren Dale, Kim, Jinwoo, Lim, Sung Kyu, Swaminathan, Madhavan

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  5. 5
    The IEEE EPS Packaging Benchmark Suite

    The IEEE EPS Packaging Benchmark Suite by Guo, Fei, Aygun, Kemal, Becker, W. Dale, Talocia, Stefano Grivet, Hejase, Jose A., Wong, Wui-Weng, Zhou, Tingdong, Barnes, Heidi, Peng, Zhen, Pelger, Alexander, Sahouli, Mohamed, Schutt-Aine, Jose, Ling, Feng, Griese, Elmar, Paladhi, Pavel Roy, Sharma, Rohit, Pham, Nam, Winkel, Thomas-Michael, Fledell, Evan, Hill, Michael J., Silva, Benjamin, Hu, Kaisheng, Aronsson, Jonatan, Liu, Chang, Jeong, Yiru, Yilmaz, Ali E.

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  6. 6
    Modeling and analysis of package PDN for computing system based on cavity model

    Modeling and analysis of package PDN for computing system based on cavity model by Jonghyun Cho, Siqi Bai, Biyao Zhao, Ruehli, Albert, Drewniak, James, Cocchini, Matteo, Connor, Samuel, Cracraft, Michael A., Becker, Dale

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  7. 7
    Physics-Based Circuit Modeling Methodology for System Power Integrity Analysis and Design

    Physics-Based Circuit Modeling Methodology for System Power Integrity Analysis and Design by Zhao, Biyao, Bai, Siqi, Connor, Samuel, Becker, Wiren Dale, Cocchini, Matteo, Cho, Jonghyun, Ruehli, Albert, Archambeault, Bruce, Drewniak, James L.

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  8. 8
    Foreword: Special Section on Addressing Signal and Power Integrity in Future Generation Systems-Part 2: Modeling Considerations

    Foreword: Special Section on Addressing Signal and Power Integrity in Future Generation Systems-Part 2: Modeling Considerations by Becker, Wiren Dale, Grivet-Talocia, Stefano

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  9. 9
    Foreword: Special Section on Addressing Signal and Power Integrity in Future Generation Systems-Part I: Technology and Design Considerations

    Foreword: Special Section on Addressing Signal and Power Integrity in Future Generation Systems-Part I: Technology and Design Considerations by Becker, Wiren Dale, Grivet-Talocia, Stefano

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  10. 10
    Inductance Calculation for the Power Net Area Fill of Packages and PCBs Based on Plane-Pair PEEC

    Inductance Calculation for the Power Net Area Fill of Packages and PCBs Based on Plane-Pair PEEC by Bai, Siqi, Connor, Samuel, Becker, Wiren Dale, Archambeault, Bruce, Ruehli, Albert E.

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  11. 11
    Reference Clock Assessment Techniques for PCIe Gen5 and Beyond

    Reference Clock Assessment Techniques for PCIe Gen5 and Beyond by Doyle, Matthew, Berge, Layne, Becker, Dale, Cocchini, Matteo, Bjorgaard, Jason

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  12. 12
    Polynomial Chaos modeling for jitter estimation in high-speed links

    Polynomial Chaos modeling for jitter estimation in high-speed links by Dolatsara, Majid Ahadi, Yu, Huan, Hejase, Jose Ale, Becker, Wiren Dale, Swaminathan, Madhavan

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  13. 13
    A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network

    A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network by Krishna, Ram, Nguyen, Thong, Watanabe, Atom O., Becker, Dale, Kumar, Arvind, Rosenbaum, Elyse

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  14. 14
    Impacts of Anisotropic Permittivity on PCB Trace and Via Modeling

    Impacts of Anisotropic Permittivity on PCB Trace and Via Modeling by Zhao, Biyao, Chen, Zhaoqing, Becker, Dale

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  15. 15
    Evaluation of the critical thermal maximum for determining thermal tolerance of freshwater fish

    Evaluation of the critical thermal maximum for determining thermal tolerance of freshwater fish by Becker, C. Dale, Genoway, Robert G.

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  16. 16
    Invertible Neural Networks for Inverse Design of CTLE in High-speed Channels

    Invertible Neural Networks for Inverse Design of CTLE in High-speed Channels by Dolatsara, Majid Ahadi, Yu, Huan, Hejase, Jose Ale, Dale Becker, Wiren, Swaminathan, Madhavan

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  17. 17
    Past and present water-quality conditions in the Hanford Reach, Columbia River

    Past and present water-quality conditions in the Hanford Reach, Columbia River by BECKER, C. D, GRAY, R. H

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  18. 18
    Dual-Band Monopole Antenna Feeds for Substrate Integrated Waveguides

    Dual-Band Monopole Antenna Feeds for Substrate Integrated Waveguides by Paladhi, Pavel Roy, Hejase, Jose, Tang, Junyan, Myers, Joshua, Chun, Sungjun, Becker, Dale, Dreps, Daniel

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  19. 19
    OpenCAPI Memory Interface Simulation and Test for Differential DIMM Channel with SNIA SFF-TA-1002 Connector

    OpenCAPI Memory Interface Simulation and Test for Differential DIMM Channel with SNIA SFF-TA-1002 Connector by Car, Biao, Hejase, Jose, Mcilvain, Kevin, Giesen, Kyle, Chen, Zhaoqin, Zhang, Hongqing, Tang, Junyan, Nguyen, Megan, Baughen, Devon, Dreps, Daniel, Connolly, Brian, Wiedemeier, Glen, Becker, Dale, Chun, Sungjun, Beaman, Brian, Fan, Zhineng, Huang, Yifan, Wander, Abhijit, Mahran, Victor

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  20. 20
    Package and Printed Circuit Board Design of a 19.2 Gb/s Data Link for High-Performance Computing

    Package and Printed Circuit Board Design of a 19.2 Gb/s Data Link for High-Performance Computing by Sungjun Chun, Hejase, Jose, Tang, Junyan, Audet, Jean, Becker, Dale, Dreps, Daniel, Wiedemeier, Glen, Nguyen, Megan, Walls, Lloyd, Preda, Francesco, Douriet, Daniel

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