On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells by Mazurier, J., Weber, O., Andrieu, F., Toffoli, A., Rozeau, O., Poiroux, T., Allain, F., Perreau, P., Fenouillet-Beranger, C., Thomas, O., Belleville, M., Faynot, O.

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Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits by Chairat, Soundous, Beigne, Edith, Miro-Panades, Ivan, Belleville, Marc

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Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications by Houri, Samer, Billiot, Gerard, Belleville, Marc, Valentian, Alexandre, Fanet, Herve

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Advanced CAD methodology for history effect characterization in partially depleted SOI libraries by Liot, Vincent, Flatresse, Philippe, Fournier, Jean Michel, Belleville, Marc

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Designing digital circuits with nano-scale devices: Challenges and opportunities by Belleville, Marc, Thomas, Olivier, Valentian, Alexandre, Clermidy, Fabien

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Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era by Todri-Sanial, Aida, Mohanty, Saraju, Comte, Mariane, Belleville, Marc

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Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology by Thomas, Olivier, Reyboz, Marina, Belleville, Marc

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An efficient metric of setup time for pulsed flip-flops based on output transition time by Bernard, Sebastien, Valentian, Alexandre, Belleville, Marc, Bol, David, Legat, Jean-Didier

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On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells : CHARACTERIZATION OF NANO CMOS VARIABIALITY BY SIMULATION AND MEASUREMENTS by MAZURIER, Jérôme, WEBER, Olivier, BELLEVILLE, Marc, FAYNOT, Olivier, ANDRIEU, François, TOFFOLI, Alain, ROZEAU, Olivier, POIROUX, Thierry, ALLAIN, Fabienne, PERREAU, Pierre, FENOUILLET-BERANGER, Claire, THOMAS, Olivier

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A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits by Joshi, Smriti, Lombardot, Anne, Belleville, Marc, Beigne, Edith, Girard, Stephane

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Design challenges for nano-scale devices by Belleville, M., Thomas, O., Valentian, A., Clermidy, F.

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Design of a robust and ultra-low-voltage pulse-triggered flip-flop in 28nm UTBB-FDSOI technology by Bernard, Sebastien, Valentian, Alexandre, Belleville, Marc, Bol, David, Legat, Jean-Didier

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A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing by Soussan, D., Valentian, A., Majcherczak, S., Belleville, M.

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A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits by Onkaraiah, Santhosh, Belleville, Marc, Reyboz, Marina, Clermidy, Fabien, Vianello, Elisa, Portal, Jean-Michel, Muller, Christophe

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A low jitter active body-biasing control-based output buffer in 65nm PD-SOI by Soussan, D, Majcherczak, S, Valentian, A, Belleville, M

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Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI by Bernard, Sébastien, Belleville, Marc, Legat, Jean-Didier, Valentian, Alexandre, Bol, David

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Statistical leakage modeling in CMOS logic gates considering process variations by D'Agostino, C., Flatresse, P., Beigne, E., Belleville, M.

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Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec by Le Coz, J, Flatresse, P, Engels, S, Valentian, A, Belleville, M, Raynaud, C, Croain, D, Urard, P

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An innovative timing slack monitor for variation tolerant circuits by Rebaud, B., Belleville, M., Beigne, E., Robert, M., Maurine, P., Azemard, N.

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An accurate approach for statistical estimation of leakage current considering multi-parameter process variations in nanometer CMOS technologies by D'Agostino, C., Le Coz, J., Flatresse, P., Beigne, E., Belleville, M.

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