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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
by
OH, Tae-Young
,
SOHN, Young-Soo
,
KIM, Jin-Hyun
,
KIM, Jin-Kook
,
KIM, Young-Sik
,
KIM, Byeong-Cheol
,
KWAK, Sang-Hyup
,
LEE, Jae-Hyung
,
LEE, Jae-Young
,
SHIN, Chang-Ho
,
YANG, Yunseok
,
CHO, Beom-Sig
,
BAE, Seung-Jun
,
BANG, Sam-Young
,
YANG, Hyang-Ja
,
CHOI, Young-Ryeol
,
MOON, Gil-Shin
,
PARK, Cheol-Goo
,
HWANG, Seok-Won
,
LIM, Jeong-Don
,
PARK, Kwang-Ii
,
JOO SUN CHOI
,
JUN, Young-Hyun
,
PARK, Min-Sang
,
LIM, Ji-Hoon
,
CHO, Yong-Ki
,
KIM, Dae-Hyun
,
KIM, Dong-Min
,
KIM, Hye-Ran
,
KIM, Hyun-Joong
Published in
IEEE journal of solid-state circuits
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A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
by
Tae-Young Oh
,
Young-Soo Sohn
,
Seung-Jun Bae
,
Min-Sang Park
,
Ji-Hoon Lim
,
Yong-Ki Cho
,
Dae-Hyun Kim
,
Dong-Min Kim
,
Hye-Ran Kim
,
Hyun-Joong Kim
,
Jin-Hyun Kim
,
Jin-Kook Kim
,
Young-Sik Kim
,
Byeong-Cheol Kim
,
Sang-Hyup Kwak
,
Jae-Hyung Lee
,
Jae-Young Lee
,
Chang-Ho Shin
,
Yun-Seok Yang
,
Beom-Sig Cho
,
Sam-Young Bang
,
Hyang-Ja Yang
,
Young-Ryeol Choi
,
Gil-Shin Moon
,
Cheol-Goo Park
,
Seok-Won Hwang
,
Jeong-Don Lim
,
Kwang-Il Park
,
Joo Sun Choi
,
Young-Hyun Jun
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Ieee Journal Of Solid-State Circuits
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Delay
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Jitter
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Sdram
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Active Control
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Active Jitter Canceller
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Applied Sciences
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Bandwidth
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Bank Group
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Bank To Bank Active Time
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Banks
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Bitline Sense Amplifier Enable
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Boosting
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Charge Pumps
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Circuit Properties
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Constrictions
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Core Cycle
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Dynamic Random Access Memory
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Electric, Optical And Optoelectronic Circuits
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Electrical Engineering. Electrical Power Engineering
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