Search Results - Bezati, Endri

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  1. 1
    Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

    Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs by Prihozhy, Anatoly, Casale-Brunet, Simone, Bezati, Endri, Mattavelli, Marco

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  2. 2
    Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

    Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs by Roquier, Ghislain, Bezati, Endri, Mattavelli, Marco

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  3. 3
    Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

    Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs by Bezati, Endri, Casale-Brunet, Simone, Mattavelli, Marco, Janneck, Jorn W.

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  4. 4
    An Heterogeneous Compiler of Dataflow Programs for Zynq Platforms

    An Heterogeneous Compiler of Dataflow Programs for Zynq Platforms by Bezati, Endri, Casale-Brunet, Simone, Mosqueron, Romuald, Mattavelli, Marco

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  5. 5
    Automated Design Flow for Multi-Functional Dataflow-Based Platforms

    Automated Design Flow for Multi-Functional Dataflow-Based Platforms by Sau, Carlo, Meloni, Paolo, Raffo, Luigi, Palumbo, Francesca, Bezati, Endri, Casale-Brunet, Simone, Mattavelli, Marco

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  6. 6
    High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

    High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms by Bezati, Endri, Thavot, Richard, Roquier, Ghislain, Mattavelli, Marco

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  7. 7
    High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

    High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs by Michalska, Magorzata, Casale-Brunet, Simone, Bezati, Endri, Mattavelli, Marco

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  8. 8
    Profiling of dynamic dataflow programs on MPSoC multi-core architectures

    Profiling of dynamic dataflow programs on MPSoC multi-core architectures by Brunet, Simone Casale, Bezati, Endri, Bloch, Aurelien, Mattavelli, Marco

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  9. 9
    Methods to explore design space for MPEG RMC codec specifications

    Methods to explore design space for MPEG RMC codec specifications by Casale-Brunet, Simone, Elguindy, Abdallah, Bezati, Endri, Thavot, Richard, Roquier, Ghislain, Mattavelli, Marco, Janneck, Jorn W.

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  10. 10
    Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

    Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs by Prihozhy, Anatoly, Bezati, Endri, Al-Hadi Ab Rahman, Ab, Mattavelli, Marco

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  11. 11
    Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs

    Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs by Michalska, Małgorzata, Casale-Brunet, Simone, Bezati, Endri, Mattavelli, Marco

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  12. 12
    High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms: Design and Architectures of Real-Time Image Processing in Embedded Systems

    High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms: Design and Architectures of Real-Time Image Processing in Embedded... by BEZATI, Endri, THAVOT, Richard, ROQUIER, Ghislain, MATTAVELLI, Marco

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  13. 13
    Live demonstration: High level software and hardware synthesis of dataflow programs

    Live demonstration: High level software and hardware synthesis of dataflow programs by Bezati, Endri, Roquier, Ghislain, Mattavelli, Marco

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  14. 14
    Methods to explore design space for MPEG RVC codec specifications

    Methods to explore design space for MPEG RVC codec specifications by Mattavelli, Marco, Brunet, Simone Casale, Elguindy, Abdallah A. A., Bezati, Endri, Thavot, Richard, Roquier, Ghislain, Janneck, Jörn

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  15. 15
    Dataflow machines

    Dataflow machines by Janneck, Jorn W., Cerdersjo, Gustav, Bezati, Endri, Brunet, Simone Casale

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  16. 16
    Generating hardware and software for RISC-V cores generated with Rocket Chip generator

    Generating hardware and software for RISC-V cores generated with Rocket Chip generator by Savas, Suleyman, Bezati, Endri, Janneck, Jorn W.

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  17. 17
    High-level synthesis of dataflow programs for signal processing systems

    High-level synthesis of dataflow programs for signal processing systems by Bezati, Endri, Mattavelli, Marco, Janneck, Jorn W.

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  18. 18
    StreamBlocks: A compiler for heterogeneous dataflow computing (technical report)

    StreamBlocks: A compiler for heterogeneous dataflow computing (technical report) by Bezati, Endri, Emami, Mahyar, Janneck, Jörn, Larus, James

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  19. 19
    Towards in the Field Fast Pathogens Detection Using FPGAs

    Towards in the Field Fast Pathogens Detection Using FPGAs by Casale Brunet, Simone, Schuepbach, Thierry, Guex, Nicolas, Iseli, Christian, Bridge, Alan, Kuznetsov, Dmitry, Sigrist, Christian, Lemercier, Philippe, Xenarios, Ioannis, Bezati, Endri

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  20. 20
    RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding

    RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding by Bezati, Endri, Mattavelli, Marco, Raulet, Mickael

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