Convolution neural network inference using frequency modulation in computational phase-change memory by Trabelsi, A., Cagli, C., Hirtzlin, T., Martin, S., Billoint, O., Vianello, E., Sousa, V., Bourgeois, G., Andrieu, F.

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3DVLSI with CoolCube process: An alternative path to scaling by Batude, P., Fenouillet-Beranger, C., Pasini, L., Lu, V., Deprat, F., Brunet, L., Sklenard, B., Piegas-Luce, F., Casse, M., Mathieu, B., Billoint, O., Cibrario, G., Turkyilmaz, O., Sarhan, H., Thuries, S., Hutin, L., Sollier, S., Widiez, J., Hortemel, L., Tabone, C., Samson, M.-P, Previtali, B., Rambal, N., Ponthenier, F., Mazurier, J., Beneyton, R., Bidaud, M., Josse, E., Petitprez, E., Rozeau, O., Rivoire, M., Euvard-Colnat, C., Seignard, A., Fournel, F., Benaissa, L., Coudrain, P., Leduc, P., Hartmann, J.-M, Besson, P., Kerdiles, S., Bout, C., Nemouchi, F., Royer, A., Agraffeil, C., Ghibaudo, G., Signamarcheix, T., Haond, M., Clermidy, F., Faynot, O., Vinet, M.

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A comprehensive study of Monolithic 3D cell on cell design using commercial 2D tool by Billoint, O., Sarhan, H., Rayane, I., Vinet, M., Batude, P., Fenouillet-Beranger, C., Rozeau, O., Cibrario, G., Deprat, F., Fustier, A., Michallet, J-E, Faynot, O., Turkyilmaz, O., Christmann, J-F, Thuries, S., Clermidy, F.

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Hybrid FeRAM/RRAM Synaptic Circuit Enabling On-Chip Inference and Learning at the Edge by Martemucci, M., Rummens, F., Hirtzlin, T., Martin, S., Guille, O., Januel, T., Carabasse, C., Billoint, O., Laguerre, J., Coignus, J., Vincent, A. F., Querlioz, D., Grenouillet, L., Saighi, S., Vianello, E.

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OxRAM for embedded solutions on advanced node: scaling perspectives considering statistical reliability and design constraints by Sandrini, J., Barlas, M., Nodin, J. F., Billoint, O., Molas, G., Fournel, R., Nowak, E., Gaillard, F., Cagli, C., Grenouillet, L., Meli, V., Castellani, N., Hammad, I., Bernasconi, S., Aussenac, F., Van Duijn, S., Audoit, G.

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A Multi-channel platform for recording and stimulation of large neuronal structures by Guillemaud, R, Bêche, J.-F, Billoint, O, Bonnet, S, Gharbi, S, Rostaing, J.-P, Trévisiol, M, Yvert, B, Rousseau, L, Goy, F, Heuschkel, M, David, O, Saillet, S, Charvet, G

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UTBB FDSOI technology flexibility for ultra low power internet-of-things applications by Beigne, E., Christmann, J.-F, Valentian, A., Billoint, O., Amat, E., Morche, D.

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FDSOI Suitability for Asynchronous Circuits at Sub-VT by Amat, Esteve, Christmann, Jean-Frédéric, Billoint, Olivier, Miro, Ivan, Beigne, Edith

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Optimization of RRAM and OTS selector for advanced low voltage CMOS compatibility by Lopez, J. Minguet, Alfaro Robayo, D., Grenouillet, L., Carabasse, C., Navarro, G., Fournel, R., Sabbione, C., Bernard, M., Billoint, O., Cagli, C., Couture, L., Deleruyelle, D., Bocquet, M., Portal, J. M., Nowak, E., Molas, G.

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Opportunities and challenges brought by 3D-sequential integration by Batude, P., Brunet, L., Fenouillet-Beranger, C., Lattard, D., Andrieu, F., Vinet, M., Brevard, L., Ribotta, M., Previtali, B., Tabone, C., Ponthenier, F., Rambal, N., Sideris, P., Garros, X., Casse, M., Theodorou, C., Sklenard, B., Lacord, J., Besson, P., Fournel, F., Kerdiles, S., Acosta-Alba, P., Mazzocchi, V., Hartmann, J-M., Mazen, F., Thuries, S., Billoint, O., Vivet, P., Sicard, G., Cibrario, G., Mouhdach, M., Giraud, B., Ribotta, CM, Lapras, V.

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3D sequential integration: applications and associated key enabling modules (design & technology) by Batude, P., Billoint, O., Thuries, S., Malinge, P., Fenouillet-Beranger, C., Peizerat, A., Sicard, G., Vivet, P., Reboh, S., Cavalcante, C., Brunet, L., Ribotta, M., Brevard, L., Garros, X., Frutuoso, T. Mota, Sklenard, B., Lacord, J., Kanyandekwe, J., Kerdiles, S., Sideris, P., Theodorou, C., Lapras, V., Mouhdach, M., Gaudin, G., Besnard, G., Radu, I., Ponthenier, F., Farcy, A., Jesse, E., Guyader, F., Matheret, T., Brunet, P., Milesi, F., Van-Jodin, L. Le, Sarrazin, A., Perrin, B., Moulin, C., Maitrejean, S., Alepidis, M., Ionica, I., Cristoloveanu, S., Gaillard, F., Vinet, M., Andrieu, F., Arcamone, J., Ollier, E.

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Monolithic 3D integration: A powerful alternative to classical 2D scaling by Vinet, M., Batude, P., Fenouillet-Beranger, C., Clermidy, F., Brunet, L., Rozeau, O., Hartmannn, Jm, Billoint, O., Cibrario, G., Previtali, B., Tabone, C., Sklenard, B., Turkyilmaz, O., Ponthenier, F., Rambal, N., Samson, Mp, Deprat, F., Lu, V., Pasini, L., Thuries, S., Sarhan, H., Michallet, J.-E, Faynot, O.

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(Invited) Direct Bonding: A Key Enabler for 3D Monolithic Integration by Brunet, Laurent, Batude, Perrine, Fournel, Frank, Benaissa, Lamine, Fenouillet-Beranger, Claire, Pasini, Luca, Deprat, Fabien, Previtali, Bernard, Ponthenier, Fabienne, Seignard, Aurélien, Euvrard-Colnat, Catherine, Rivoire, Maurice, Besson, Pascal, Arvet, Christian, Beche, Elodie, Rozeau, Olivier, Billoint, Olivier, Turkyilmaz, Ogun, Clermidy, Fabien, Signamarcheix, Thomas, Vinet, Maud

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Impact of intermediate BEOL technology on standard cell performances of 3D VLSI by Brocard, M., Berhault, G., Thuries, S., Clermidy, F., Batude, P., Fenouillet-Beranger, C., Brunet, L., Andrieu, F., Deprat, F., Lacord, J., Rozeau, O., Cibrario, G., Billoint, O.

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Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation by Andrieu, F., Berthelon, R., Boumchedda, R., Tricaud, G., Brunet, L., Batude, P., Mathieu, B., Avelar, E., de Sousa, A. Ayres, Cibrario, G., Rozeau, O., Lacord, J., Billoint, O., Fenouillet-Beranger, C., Guissi, S., Fried, D., Morin, P., Noel, J. P., Giraud, B., Thuries, S., Arnaud, F., Vinet, M.

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New perspectives for multicore architectures using advanced technologies by Clermidy, F., Vivet, P., Dutoit, D., Thonnart, Y., Gonzales, J. L., Noel, J. P., Giraud, B., Levisse, A., Billoint, O., Thuries, S.

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Distributed clock generator for synchronous SoC using ADPLL network by Zianbetov, E., Akre, J- M., Juillard, J., Galayko, D., Anceau, F., Javidan, M., Shan, C., Billoint, O., Korniienko, A., Colinet, E., Scorletti, G.

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Ultra-Wide Voltage Range designs in Fully-Depleted Silicon-On-Insulator FETs by Beigne, E., Valentian, A., Giraud, B., Thomas, O., Benoist, T., Thonnart, Y., Bernard, S., Moritz, G., Billoint, O., Maneglia, Y., Flatresse, P., Noel, J.P., Abouzeid, F., Pelloux-Prayer, B., Grover, A., Clerc, S., Roche, P., Le Coz, J., Engels, S., Wilson, R.

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A modular 256-channel Micro Electrode Array platform for in vitro and in vivo neural stimulation and recording: BioMEA by Charvet, G, Billoint, O, Gharbi, S, Heuschkel, M, Georges, C, Kauffmann, T, Pellissier, A, Yvert, B, Guillemaud, R

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A 64-Channel ASIC for In-Vitro Simultaneous Recording and Stimulation of Neurons using Microelectrode Arrays by Billoint, O., Rostaing, J.P., Charvet, G., Yvert, B.

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