Search Results - Bindra, Harijot Singh

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  1. 1
    A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

    A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation by Shen, Yuting, Li, Hanyue, Bindra, Harijot Singh, Cantatore, Eugenio, Harpe, Pieter

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  2. 2
    Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging

    Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging by Lechevallier, Joeri B., Bindra, Harijot Singh, van der Zee, Ronan A. R., Nauta, Bram

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  3. 3
    Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates

    Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates by Huiskamp, Maikel, Alink, Mark S. Oude, Nauta, Bram, Annema, Anne-Johan, Bindra, Harijot Singh

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  4. 4
    A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

    A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise by Bindra, Harijot Singh, Lokin, Christiaan E., Schinkel, Daniel, Annema, Anne-Johan, Nauta, Bram

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  5. 5
    A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection

    A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection by Ramkumar, Viswesh Kendae, Huiskamp, Maikel, Bindra, Harijot Singh, Klumperink, Eric, Nauta, Bram

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  6. 6
    A 174μVRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch

    A 174μVRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch by Bindra, Harijot Singh, Ponte, Jeroen, Nauta, Bram

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  7. 7
    A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

    A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply by Bindra, Harijot Singh, Annema, Anne-Johan, Wienk, Gerard, Nauta, Bram, Louwsma, Simon M.

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  8. 8
    Clock and data recovery module in 90nm for 10Gbps serial link with −18dB channel attenuation

    Clock and data recovery module in 90nm for 10Gbps serial link with −18dB channel attenuation by Bindra, Harijot Singh, Chatterjee, Shouri, Saha, Kaushik, Kukal, Taranjit

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  9. 9
    A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

    A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator by Bindra, Harijot Singh, Annema, Anne-Johan, Louwsma, Simon M., Nauta, Bram

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