Area-efficient linear regulator with ultra-fast load regulation by Hazucha, P., Karnik, T., Bloechel, B.A., Parsons, C., Finan, D., Borkar, S.

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Dynamic sleep transistor and body bias for active leakage power control of microprocessors by Tschanz, J.W., Narendra, S.G., Ye, Y., Bloechel, B.A., Borkar, S., De, V.

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A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package by Hazucha, P., Schrom, G., Jaehong Hahn, Bloechel, B.A., Hack, P., Dermer, G.E., Narendra, S., Gardner, D., Karnik, T., De, V., Borkar, S.

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Forward body bias for microprocessors in 130-nm technology generation and beyond by Narendra, S., Keshavarzi, A., Bloechel, B.A., Borkar, S., De, V.

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A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS by Hoskote, Y., Bloechel, B.A., Dermer, G.E., Erraguntla, V., Finan, D., Howard, J., Klowden, D., Narendra, S.G., Ruhl, G., Tschanz, J.W., Sriram Vangal, Veeramachaneni, V., Wilson, H., Jianping Xu, Borkar, N.

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Accurate on-chip interconnect evaluation: a time-domain technique by Soumyanath, K., Borkar, S., Chunyan Zhou, Bloechel, B.A.

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5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS by Vangal, S, Anders, M.A, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Tschanz, J.W, Ye, Y, Somasekhar, D, Bloechel, B.A, Dermer, G.E, Krishnamurthy, R.K, Soumyanath, K, Mathew, S, Narendra, S.G, Stan, M.R, Thompson, S, De, V, Borkar, S

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process by Hazucha, P., Karnik, T., Walstra, S., Bloechel, B.A., Tschanz, J.W., Maiz, J., Soumyanath, K., Dermer, G.E., Narendra, S., De, V., Borkar, S.

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, BA, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, GE, Narendra, S, De, V, Borkar, S

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Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process by HAZUCHA, Peter, KARNIK, Tanay, BORKAR, Shekhar, WALSTRA, Steven, BLOECHEL, Bradley A, TSCHANZ, James W, MAIZ, Jose, SOUMYANATH, Krishnamurthy, DERMER, Gregory E, NARENDRA, Siva, DE, Vivek

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64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method by Franca-Neto, L.M., Bishop, R.E., Bloechel, B.A.

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5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS by Vangal, S., Anders, M.A., Borkar, N., Seligman, E., Govindarajulu, V., Erraguntla, V., Wilson, H., Pangal, A., Veeramachaneni, V., Tschanz, J.W., Ye, Y., Somasekhar, D., Bloechel, B.A., Dermer, G.E., Krishnamurthy, R.K., Soumyanath, K., Mathew, S., Narendra, S.G., Stan, M.R., Thompson, S., De, V., Borkar, S.

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A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control by Schrom, G., Hazucha, P., Hahn, J., Gardner, D.S., Bloechel, B.A., Dermer, G., Narendra, S.G., Karnik, T., De, V.

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17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18/spl mu/m logic CMOS technology by Franca-Neto, L.M., Bloechel, B.A., Soumyanath, K.

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