Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors by Qingda Lu, Alias, C., Bondhugula, U., Henretty, T., Krishnamoorthy, S., Ramanujam, J., Rountev, A., Sadayappan, P., Yongjian Chen, Haibo Lin, Ngai, T.-f.

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Tiling stencil computations to maximize parallelism by Bandishti, V., Pananilath, I., Bondhugula, U.

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Parallel FPGA-based all-pairs shortest-paths in a directed graph by Bondhugula, U., Devulapalli, A., Fernando, J., Wyckoff, P., Sadayappan, P.

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Towards effective automatic parallelization for multicore systems by Bondhugula, U., Baskaran, M., Hartono, A., Krishnamoorthy, S., Ramanujam, J., Rountev, A., Sadayappan, P.

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Compact multi-dimensional kernel extraction for register tiling by Renganarayana, L., Bondhugula, U., Derisavi, S., Eichenberger, A. E., O'Brien, K.

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Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths by Bondhugula, U., Devulapalli, A., Dinan, J., Fernando, J., Wyckoff, P., Stahlberg, E., Sadayappan, P.

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