Impact of laser anneal on NiPt silicide texture and chemical composition by Feautrier, C., Ozcan, A. S., Lavoie, C., Valery, A., Beneyton, R., Borowiak, C., Clément, L., Pofelski, A., Salem, B.

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Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below by Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.

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Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology by Fenouillet-Beranger, C., Perreau, P., Benoist, T., Richier, C., Haendler, S., Pradelle, J., Bustos, J., Brun, P., Tosti, L., Weber, O., Andrieu, F., Orlando, B., Pellissier-Tanon, D., Abbate, F., Richard, C., Beneyton, R., Gregoire, M., Ducote, J., Gouraud, P., Margain, A., Borowiak, C., Bianchini, R., Planes, N., Gourvest, E., Bourdelle, K.K., Nguyen, B.Y., Poiroux, T., Skotnicki, T., Faynot, O., Boeuf, F.

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Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances by Ben Akkez, Imed, Fenouillet-Beranger, Claire, Cros, Antoine, Perreau, Pierre, Haendler, Sébatien, Weber, Olivier, Andrieu, François, Pellissier-Tanon, D., Abbate, F., Richard, C., Beneyton, R., Gouraud, P., Margain, A., Borowiak, C., Gourvest, E., Bourdelle, K.K., Nguyen, B.Y., Poiroux, T., Skotnicki, Thomas, Faynot, Olivier, Balestra, Francis, Ghibaudo, Gérard, Boeuf, Fréderic

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Efficient multi-VT FDSOI technology with UTBOX for low power circuit design by Fenouillet-Beranger, C, Thomas, O, Perreau, P, Noel, J.-P, Bajolet, A, Haendler, S, Tosti, L, Barnola, S, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Baron, F, Pernet, B, Campidelli, Y, Pinzelli, L, Gouraud, P, Cassé, M, Borowiak, C, Weber, O, Andrieu, F, Denorme, S, Boeuf, F, Faynot, O, Skotnicki, T, Bourdelle, K K, Nguyen, B Y, Boedt, F

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Microscopy needs for next generation devices characterization in the semiconductor industry by Clement, L, Borowiak, C, Galand, R, Lepinay, K, Lorut, F, Pantel, R, Servanton, G, Thomas, R, Vannier, P, Bicais, N

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Farmers’ Rights: Intellectual Property Regimes and the Struggle over Seeds by Borowiak, Craig

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Impact of laser anneal on NiPt silicide texture and chemical composition by Feautrier, C., Ozcan, A. S., Lavoie, C., Valery, A., Beneyton, R., Borowiak, C., Clément, L., Pofelski, A., Salem, B.

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Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below by Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.

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Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation Integration by Berthelon, R., Weber, O., Ibars, F., Revel, B., Borowiak, C., Grenier, J.C., Dumont, B., Desmoulins, S., Sassoulas, P.O., Ferreira, P., Chouteau, S., Niel, S., Ranica, R., Gonella, R., Arnaud, F.

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Crystallization study of "melt quenched" amorphous GeTe by transmission electron microscopy for phase change memory applications by Bastard, A., Bastien, J. C., Hyot, B., Lhostis, S., Mompiou, F., Bonafos, C., Servanton, G., Borowiak, C., Lorut, F., Bicais-Lepinay, N., Toffoli, A., Sandhya, C., Fantini, A., Perniola, L., Gourvest, E., Maitrejean, S., Roule, A., Sousa, V., Bensahel, D., André, B.

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Hybrid Localized SOI/bulk technology for low power system-on-chip by Huguenin, J.-L, Monfray, S, Bidal, G, Denorme, S, Perreau, P, Barnola, S, Samson, M.-P, Arvet, C, Benotmane, K, Loubet, N, Liu, Q, Campidelli, Y, Leverd, F, Abbate, F, Clement, L, Borowiak, C, Cros, A, Bajolet, A, Handler, S, Marin-Cudraz, D, Benoist, T, Galy, P, Fenouillet-Beranger, C, Faynot, O, Ghibaudo, G, Boeuf, F, Skotnicki, T

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Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology: Selected extended papers from ULIS 2012 conference by FENOUILLET-BERANGER, C, PERREAU, P, ANDRIEU, F, ORLANDO, B, PELLISSIER-TANON, D, ABBATE, F, RICHARD, C, BENEYTON, R, GREGOIRE, M, DUCOTE, J, GOURAUD, P, MARGAIN, A, BENOIST, T, BOROWIAK, C, BIANCHINI, R, PLANES, N, GOURVEST, E, BOURDELLE, K. K, NGUYEN, B. Y, POIROUX, T, SKOTNICKI, T, FAYNOT, O, BOEUF, F, RICHIER, C, HAENDLER, S, PRADELLE, J, BUSTOS, J, BRUN, P, TOSTI, L, WEBER, O

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Against Ecofeminism: Agrarian Populism and the Splintered Subject in Rural India by Roy, Tania, Borowiak, Craig

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Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below by Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.

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Impact of 45° rotated substrate on UTBOX FDSOI high-k metal gate technology by Ben Akkez, I., Fenouillet-Beranger, C., Cros, A., Perreau, P., Haendler, S., Weber, O., Andrieu, F., Pellissier-Tanon, D., Abbate, F., Richard, C., Beneyton, R., Gouraud, P., Margain, A., Borowiak, C., Gourvest, E., Bourdelle, K. K., Nguyen, B. Y., Poiroux, T., Skotnicki, T., Faynot, O., Balestra, F., Ghibaudo, G., Boeuf, F.

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A solution for an ideal planar multi-gates process for ultimate CMOS? by Monfray, S, Huguenin, J, Martin, M, Samson, M, Borowiak, C, Arvet, C, Dalemcourt, J, Perreau, P, Barnola, S, Bidal, G, Denorme, S, Campidelli, Y, Benotmane, K, Leverd, F, Gouraud, P, Le-Gratiet, B, De-Buttet, C, Pinzelli, L, Beneyton, R, Morel, T, Wacquez, R, Bustos, J, Icard, B, Pain, L, Barraud, S, Ernst, T, Boeuf, F, Faynot, O, Skotnicki, T

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Localized SOI logic and bulk I/O devices co-integration for Low power System-on-Chip technology by Huguenin, J.-L, Monfray, S, Denorme, S, Bidal, G, Perreau, P, Barnola, S, Samson, M.-P, Benotmane, K, Loubet, N, Campidelli, Y, Leverd, F, Abbate, F, Clement, L, Borowiak, C, Golanski, D, Fenouillet-Beranger, C, Boeuf, F, Ghibaudo, G, Skotnicki, T

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Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below by Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.

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UTBOX and ground plane combined with Al2O3 inserted in TiN gate for VT modulation in fully-depleted SOI CMOS transistors by Fenouillet-Beranger, C, Perreau, P, Casse, M, Garros, X, Leroux, C, Martin, F, Gassilloud, R, Bajolet, A, Tosti, L, Barnola, S, Andrieu, F, Weber, O, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Pernet, B, Campidelli, Y, Pinzelli, L, Gouraud, P, Huguenin, J L, Borowiak, C, Peru, S, Clement, L, Pantel, R, Bourdelle, K K, Nguyen, B Y, Boedt, F, Denorme, S, Faynot, O, Skotnicki, T, Boeuf, F

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