Two gates are better than one [double-gate MOSFET process] by Solomon, P.M., Hovel, H.J., Bucchignano, J.J., Cabral, C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K., Yoon, J.H., Babich, I.V., Treichler, J., Guarini, K.W., Kozlowski, P.M., Newbury, J.S., D'Emic, C.P., Sicina, R.M., Benedict, J., Wong, H.-S.P., Zhang, Y., Chan, K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O.

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High-Performance [Formula Omitted] -Channel MOSFETs With High-[Formula Omitted] Gate Dielectrics and [Formula Omitted]-Si Passivation by Sun, Y, Kiewra, E.W, de Souza, J.P, Bucchignano, J.J, Fogel, K.E, Sadana, D.K, Shahidi, G.G

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High-Performance \hbox\hbox\hbox -Channel MOSFETs With High- \kappa Gate Dielectrics and \alpha-Si Passivation by Sun, Y., Kiewra, E.W., de Souza, J.P., Bucchignano, J.J., Fogel, K.E., Sadana, D.K., Shahidi, G.G.

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Resistance anomaly near the superconducting transition temperature in short aluminum wires by SANTHANAM, P, CHI, C. C, WIND, S. J, BRADY, M. J, BUCCHIGNANO, J. J

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High Performance Long-and Short-Channel In0.7Ga0.3As-channel MOSFETs by Yanning Sun, Kiewra, E.W., de Souza, J.P., Bucchignano, J.J., Fogel, K.E., Sadana, D.K., Shahidi, G.G.

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High mobility III-V channel MOSFETs for post-Si CMOS applications by Yanning Sun, Kiewra, E.W., De Souza, J.P., Koester, S.J., Bucchignano, J.J., Ruiz, N., Fogel, K.E., Sadana, D.K., Shahidi, G.G., Fompeyrine, J., Webb, D.J., Sousa, M., Marchiori, C., Germann, R., Shiu, K.T.

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Triple-self-aligned, planar double-gate MOSFETs: devices and circuits by Guarini, K.W., Solomon, P.M., Zhang, Y., Chan, K.K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O., Bucchignano, J.J., Cabral, C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K.S., Babich, I.V., Treichler, J., Kozlowski, P.M., Newbury, J.S., D'Emic, C.P., Sicina, R.M., Wong, H.-S.

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Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node by Ohuchi, K., Lavoie, C., Murray, C., D'Emic, C., Chu, J.O., Bin Yang, Besser, P., Gignac, L., Bruley, J., Singco, G.U., Pagette, F., Topol, A.W., Rooks, M.J., Bucchignano, J.J., Narayanan, V., Khare, M., Takayanagi, M., Ishimaru, K., Dae-Gyu Park, Shahidi, G., Solomon, P.

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Scaling of In0.7Ga0.3As buried-channel MOSFETs by Yanning Sun, Kiewra, E.W., de Souza, J.P., Bucchignano, J.J., Fogel, K.E., Sadana, D.K., Shahidi, G.G.

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Fabrication and characterization of compact 100nm scale metal oxide semiconductor field effect transistors by Reeves, C.M., Wind, S.J., Hohn, F.J., Bucchignano, J.J., Lii, Y.T., Klaus, D.P.

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High-transconductance InGaAs/InAlAs SISFETs by Jackson, T.N., Solomon, P.M., Tischler, M.A., Pettit, G.D., Canora, F.J., DeGelormo, J.F., Bucchignano, J.J., Wind, S.J.

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Extendibility of NiPt silicide to the 22-nm node CMOS technology by Ohuchi, K., Lavoie, C., Murray, C.E., D'Emic, C.P., Lauer, I., Chu, J.O., Bin Yang, Besser, P., Gignac, L.M., Bruley, J., Singco, G.U., Pagette, F., Topol, A.W., Rooks, M.J., Bucchignano, J.J., Narayanan, V., Khare, M., Takayanagi, M., Ishimaru, K., Dae-Gyu Park, Shahidi, G., Solomon, P.M.

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On the preparation of cross-sectional TEM samples using lithographic processing and reactive ion-etching by Wetzel, J.T., Jost, M., Rishton, S.A., Fryer, P.M., Kwietniak, K.T., Klaus, D., Bucchignano, J.J., Hu, C.-K., Brown, T.J.

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Minimum critical length for superconductivity in one-dimensional wires by Chi, CC, Santhanam, P, Wind, SJ, Brady, MJ, Bucchignano, JJ

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Very high performance 50 nm CMOS at low temperature by Wind, S.J., Shi, L., Lee, K.-L., Roy, R.A., Zhang, Y., Sikorski, E., Kozlowski, P., D'emic, C., Bucchignano, J.J., Wann, H.-J., Viswanathan, R.G., Cai, J., Taur, Y.

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High-Transconductance Ingaas/Inaias Sisfets by Jackson, T.N., Solomon, P.M., Tischler, M.A., Pettit, G.D., Canora, F.J., DeGelormo, J.F., Bucchignano, J.J., Wind, S.J.

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A high performance 0.25 mu m CMOS technology by Davari, B., Chang, W.H., Wordeman, M.R., Oh, C.S., Taur, Y., Petrillo, K.E., Moy, D., Bucchignano, J.J., Ng, H.Y., Rosenfield, M.G., Hohn, F.J., Rodriguez, M.D.

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