Search Results - Byongtae Chung

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  1. 1
    Sense amplifier with offset mismatch calibration for sub 1-V DRAM core operation

    Sense amplifier with offset mismatch calibration for sub 1-V DRAM core operation by Jinyeong Moon, Byongtae Chung

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  2. 2
    A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network

    A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network by KyungHoon Kim, SangSic Yoon, KiChang Kwean, DaeHan Kwon, SunSuk Yang, MunPhil Park, YongKi Kim, ByongTae Chung

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  3. 3
    25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector

    25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector by Hyun-Woo Lee, Junyoung Song, Sang-Ah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jinyoup Cha, Jaeil Kim, Hoon Choi, Seungwook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jinhee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byongtae Chung, Sungjoo Hong

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  4. 4
    25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

    25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV by Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim, Hongjung Kim, Ju Young Kim, Young Jun Park, Jae Hwan Kim, Dae Suk Kim, Heat Bit Park, Jin Wook Shin, Jang Hwan Cho, Ki Hun Kwon, Min Jeong Kim, Jaejin Lee, Kun Woo Park, Byongtae Chung, Sungjoo Hong

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  5. 5
    A fast GDDR5 read CRC calculation circuit with read DBI operation

    A fast GDDR5 read CRC calculation circuit with read DBI operation by Sang-Sic Yoon, Bo-Kyeom Kim, Yong-Ki Kim, ByongTae Chung

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  6. 6
    Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network

    Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network by Junho Lee, Hyunseok Kim, Kimyung Kyung, Minyoung You, Hyungdong Lee, Kunwoo Park, Byongtae Chung

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  7. 7
    A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture

    A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture by Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Lee, Yosep, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yongju Kim, Youngdo Hur, Yunsaing Kim, Byongtae Chung, Yongtak Kim

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  8. 8
    High-PSRR all-digital delay locked loop with burst update mode and power noise damping scheme

    High-PSRR all-digital delay locked loop with burst update mode and power noise damping scheme by Yongju Kim, Jaemin Jang, Jinyeong Moon, Seongjun Lee, Daehan Kwon, Hongseok Choi, Geunwoo Park, Byongtae Chung

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