Search Results - Byoungkeun Son

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  1. 1
    Channel Coupling phenomenon as scaling barrier of NAND flash memory beyond 20nm node

    Channel Coupling phenomenon as scaling barrier of NAND flash memory beyond 20nm node by ChangHyun Lee, Jiyeong Hwang, Fayrushin, Albert, Hyunjung Kim, Byoungkeun Son, Youngwoo Park, Gyoyoung Jin, Eunseung Jung

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  2. 2
    High Speed and Highly Cost effective 72M bit density S3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory

    High Speed and Highly Cost effective 72M bit density S3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and... by Soon-Moon Jung, Hoon Lim, Chadong Yeo, Kunho Kwak, Byoungkeun Son, Hanbyung Park, Jonghoon Na, Jae-Joo Shim, Changmin Hong, Kinam Kim

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  3. 3
    65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications

    65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high sp... by Hoon Lim, Soon-Moon Jung, Youngseop Rah, Taehong Ha, Hanbyung Park, Chulsoon Chang, Wonsuk Cho, Jaikyun Park, Byoungkeun Son, Jaehun Jeong, Hoosung Cho, Bonghyun Choi, Kinam Kim

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  4. 4
    Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

    Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors f... by Soon-Moon Jung, Youngseop Rah, Taehong Ha, Hanbyung Park, Chulsoon Chang, Seungchul Lee, Jongho Yun, Wonsuk Cho, Hoon Lim, Jaikyun Park, Jaehun Jeong, Byoungkeun Son, Jaehoon Jang, Bonghyun Choi, Hoosung Cho, Kinam Kim

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  5. 5
    Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

    Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM by Soon-Moon Jung, Hoon Lim, Wonseok Cho, Hoosung Cho, Hatae Hong, Jaehun Jeong, Sugwoo Jung, Hanbyung Park, Byoungkeun Son, Youngchul Jang, Kinam Kim

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