SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory by Sung, S.-K., Lee, S.-H., Choi, B., Lee, J., Choe, J.-D., Cho, E., Ahn, Y., Choi, D., Lee, C.-H., Kim, D., Lee, Y.-S., Kim, S., Park, D., Ryu, B.-I.

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Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window by Ahn, Y., Choe, J.-D., Lee, J., Choi, D., Cho, E., Choi, B., Lee, S.-H., Sung, S.-K., Lee, C.-H., Cheong, S., Lee, D., Kim, S., Park, D., Ryu, B.-I.

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122 Mb High Speed SRAM Cell with 25 nm Gate Length Multi-Bridge-Channel MOSFET (MBCFET) on Bulk Si Substrate by Kim, Min Sang, Lee, S.-Y., Yoon, E.-J., Kim, Sung Min, Lian, J., Lee, K.-H., Cho, N., Lee, M.-S., Hwang, D., Lee, Y.-S., Kim, D.-W., Park, D., Ryu, B.-I.

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A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation by Oh, C., Kim, S., Kim, N., Choi, Y., Lee, K., Kim, B., Cho, N., Kim, D.-W., Park, D., Ryu, B.-I.

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Effect of a noble annealing system on nickel silicide formation by Sug-Woo Jung, Hyun-Su Kim, Eun-Ji Jung, Seong-Hwee Cheong, Jong-Ho Yun, Kwan-Jong Roh, Ja-Hum Ku, Gil-Heyun Choi, Sung-Tae Kim, U-In Chung, Joo-Tae Moon, Byung-Il Ryu

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Low Voltage Program/Erase Characteristics of Si Nanocrystal Memory with Damascene Gate FinFET on Bulk Si Wafer by Jeong-Dong Choe, Kyoung Hwan Yeo, Young Joon Ahn, Jong Jin Lee, Se-Hoon Lee, Byung Yong Choi, Suk Kang Sung, Eun Suk Cho, Choong-Ho Lee, Dong-Won Kim, Ilsub Chung, Donggun Park, Byung-Il Ryu

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Technology Breakthrough of Body-Tied FinFET for sub 50 nm NOR Flash Memory by Cho, E., Kim, T.-Y., Cho, B., Lee, C.-H., Lee, J., Fayrushin, A., Lee, C., Park, D., Ryu, B.-I.

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Charge Trapping WN Nano-dots with /or without Nitride Sub-layer for FinFET FLASH Memory by Choe, Jeong-dong, Lee, Jong Jin, Ahn, Young Joon, Lee, Se-hoon, Choi, Byung Yong, Sung, Suk Kang, Cho, Eun Suk, Kim, Seung Beom, Cheong, Seong Hwee, Lee, Choong-ho, Chung, Ilsub, Park, Kyuncharn, Park, Donggun, Ryu, Byung-il

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Front-end-of-line (FEOL) optimization for high-performance, high-reliable strained-Si MOSFETs; from virtual substrate to gate oxidation by LEE, Jong-Wook, LEE, Sun-Ghil, PARK, Seong-Geon, PARK, Hong-Bae, SON, Yong-Hoon, LEE, Young-Eun, JIN, Beom-Jun, LEE, Hye-Lan, KOO, Bon-Young, KANG, Sang-Bom, YU GYUN SHIN, CHUNG, U.-In, KIM, Young-Pil, MOON, Joo-Tae, RYU, Byung-Il, KIM, Chul-Sung, CHO, Hag-Ju, KIM, Seung-Beom, JUNG, In-Soo, LEE, Deok-Hyung, KIM, Dong-Chan, JEON, Taek-Soo

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A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology by Yoon, Jae-man, Lee, Kangyoon, Park, Seung-bae, Kim, Seong-goo, Seo, Hyoung-won, Son, Young-woong, Kim, Bong-soo, Chung, Hyun-woo, Lee, Choong-ho, Lee, Won-sok, Kim, Dong-chan, Park, Donggun, Lee, Wonshik, Ryu, Byung-il

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A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique by Yoshida, M., Kahng, J., Lee, C., Jang, S.-M., Sung, H., Kim, K., Kim, H.-J., Jung, K.-H., Yang, W., Park, D., Ryu, B.-I.

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Test structure for performance evaluation of 3 dimensional FinFETs by Young Joon Ahn, Hye Jin Cho, Hee Soo Kang, Choong-Ho Lee, Chul Lee, Jae-man Yoon, Tae Yong Kim, Eun Suk Cho, Suk-kang Sung, Donggun Park, Kinam Kim, Byung-Il Ryu

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Single-metal gate multi-bridge-channel MOSFET (MBCFET) for CMOS application by Sung-Young Lee, Min-Sang Kim, Eun-Jung Yoon, Sung-Dae Suk, Sung-Min Kim

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Biopathologic features and clinical significance of micrometatasis in the lymph node of early gastric cancer by Jo, Min Jung, Park, Ji Yeon, Song, Joon Seon, Kook, Myeong-Cherl, Ryu, Keun Won, Cho, Soo-Jeong, Lee, Jun Ho, Nam, Byung-Ho, Hong, Eun Kyung, Choi, Il Ju, Kim, Young-Woo

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Low Voltage Program/Erase Characteristics of Si Nanocrystal Memory with Damascene Gate FinFET on Bulk Si Wafer by Choe, Jeong-Dong, Yeo, Kyoung-Hwan, Ahn, Young-Joon, Lee, Jong-Jin, Lee, Se-Hoon, Choi, Byung-Yong, Sung, Suk-Kang, Cho, Eun-Suk, Lee, Choong-Ho, Kim, Dong-Won, Chung, Il-Sub, Park, Dong-Gun, Ryu, Byung-Il

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A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture by Hongil Yoon, Jae Yoon Sim, Hyun Suk Lee, Kyu Nam Lim, Jae Young Lee, Nam Jong Kim, Keum Yong Kim, Sang Man Byun, Won Suk Yang, Chang Hyun Choi, Hong Sik Jeong, Jel Hwan Yoo, Dong Il Seo, Kinam Kim, Byung Il Ryu, Chang Gyu Hwang

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8Gb MLC (multi-level cell) NAND flash memory using 63nm process technology by PARK, Jong-Ho, HUR, Sung-Hoi, KIM, Yong-Seok, PARK, Min-Cheol, CHAI, Soo-Jin, CHOI, Jung-Dal, CHUNG, U.-In, MOON, Joo-Tae, KIM, Kyeong-Tae, KIM, Kinam, RYU, Byung-Il, LEE, Joon-Hee, PARK, Jin-Taek, SEL, Jong-Sun, KIM, Jong-Won, SONG, Sang-Bin, LEE, Jung-Young, LEE, Ji-Hwon, SON, Suk-Joon

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3-dimensional nano-CMOS transistors to overcome scaling limits by Donggun Park, Kinam Kim, Byung-Il Ryu

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Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed by Kyong-Hee Joo, Xiofeng Wang, Jeong Hee Han, Seung-Hyun Lim, Seung-Jae Baik, Yong-Won Cha, Jin Wook Lee, In-Seok Yeo, Young-Kwan Cha, In Kyeong Yoo, U-In Chung, Joo Tae Moon, Byung-Il Ryu

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Highly area efficient and cost effective double stacked S3(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM by JUNG, Soon-Moon, LIM, Hoon, KIM, Sungjin, JEONG, Jaehun, CHANG, Youngchul, JANG, Jaehoon, KIM, Jonghyuk, KIM, Kinam, RYU, Byung-Il, CHO, Wonseok, CHO, Hoosung, YEO, Chadong, YONGHA KANG, BAE, Daegi, NA, Jonghoon, KWAK, Kunho, CHOI, Bonghyun

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