A 65 nm 2-Billion Transistor Quad-Core Itanium Processor by Stackhouse, B., Bhimji, S., Bostak, C., Bradley, D., Cherkauer, B., Desai, J., Francom, E., Gowan, M., Gronowski, P., Krueger, D., Morganti, C., Troyer, S.

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A 65-nm dual-core multithreaded Xeon® processor with 16-MB L3 cache by RUSU, Stefan, TAM, Simon, RAHUL DILIP LIMAYE, VORA, Sujal, MULJONO, Harry, AYERS, David, CHANG, Jonathan, CHERKAUER, Brian, STINSON, Jason, BENOIT, John, VARADA, Raj, LEUNG, Justin

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A 1.5-GHz 130-nm Itanium 2 processor with 6-MB on-die L3 cache by Rusu, S., Stinson, J., Tam, S., Leung, J., Muljono, H., Cherkauer, B.

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A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor by Stackhouse, Blaine, Cherkauer, Brian, Gowan, Mike, Gronowski, Paul, Lyles, Chris

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Itanium 2 processor 6M: higher frequency and larger L3 cache by Rusu, S., Muljono, H., Cherkauer, B.

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A unified design methodology for CMOS tapered buffers by Cherkauer, B.S., Friedman, E.G.

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Design of tapered buffers with local interconnect capacitance by Cherkauer, B.S., Friedman, E.G.

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Channel width tapering of serially connected MOSFET's with emphasis on power dissipation by Cherkauer, B.S., Friedman, E.G.

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A 65nm 95W Dual-Core Multi-Threaded Xeon® Processor with L3 Cache by Tam, S., Rusu, S., Chang, J., Vora, S., Cherkauer, B., Ayers, D.

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A hybrid radix-4/radix-8 low power signed multiplier architecture by CHERKAUER, B. S, FRIEDMAN, E. G

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The effects of channel width tapering on the power dissipation of serially connected MOSFETs by Cherkauer, B.S., Friedman, E.G.

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