An Asynchronous Power Aware and Adaptive NoC Based Circuit by Beigne, E., Clermidy, F., Lhermet, H., Miermont, S., Thonnart, Y., Xuan-Tu Tran, Valentian, A., Varreau, D., Vivet, P., Popon, X., Lebreton, H.

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A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip by Lattard, D., Beigne, E., Clermidy, F., Durand, Y., Lemaire, R., Vivet, P., Berens, F.

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Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs by Gaillardon, Pierre-Emmanuel, Sacchetto, Davide, Beneventi, Giovanni Betti, Ben Jamaa, M. Haykel, Perniola, Luca, Clermidy, Fabien, O'Connor, Ian, De Micheli, Giovanni

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Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM) by Bocquet, Marc, Aziza, Hassen, Zhao, Weisheng, Zhang, Yue, Onkaraiah, Santhosh, Muller, Christophe, Reyboz, Marina, Deleruyelle, Damien, Clermidy, Fabien, Portal, Jean-Michel

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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management by Vivet, Pascal, Guthmuller, Eric, Thonnart, Yvain, Pillonnet, Gael, Fuguet, Cesar, Miro-Panades, Ivan, Moritz, Guillaume, Durupt, Jean, Bernard, Christian, Varreau, Didier, Pontes, Julian, Thuries, Sebastien, Coriat, David, Harrand, Michel, Dutoit, Denis, Lattard, Didier, Arnaud, Lucile, Charbonnier, Jean, Coudrain, Perceval, Garnier, Arnaud, Berger, Frederic, Gueugnot, Alain, Greiner, Alain, Meunier, Quentin L., Farcy, Alexis, Arriordaz, Alexandre, Cheramy, Severine, Clermidy, Fabien

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Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster by Rossi, Davide, Pullini, Antonio, Loi, Igor, Gautschi, Michael, Gurkaynak, Frank Kagan, Teman, Adam, Constantin, Jeremy, Burg, Andreas, Miro-Panades, Ivan, Beigne, Edith, Clermidy, Fabien, Flatresse, Philippe, Benini, Luca

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SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration by Miro-Panades, Ivan, Tain, Benoit, Christmann, Jean-Frederic, Coriat, David, Lemaire, Romain, Jany, Clement, Martineau, Baudouin, Chaix, Fabrice, Waltener, Guillaume, Pluchart, Emmanuel, Noel, Jean-Philippe, Makosiej, Adam, Montoya, Maxime, Bacles-Min, Simone, Briand, David, Philippe, Jean-Marc, Thonnart, Yvain, Valentian, Alexandre, Heitzmann, Frederic, Clermidy, Fabien

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Investigation of Forming, SET, and Data Retention of Conductive-Bridge Random-Access Memory for Stack Optimization by Guy, Jeremy, Molas, Gabriel, Blaise, Philippe, Bernard, Mathieu, Roule, Anne, Le Carval, Gilles, Delaye, Vincent, Toffoli, Alain, Ghibaudo, Gerard, Clermidy, Fabien, De Salvo, Barbara, Perniola, Luca

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A Novel Programming Technique to Boost Low-Resistance State Performance in Ge-Rich GST Phase Change Memory by Kiouseloglou, Athanasios, Navarro, Gabriele, Sousa, Veronique, Persico, Alain, Roule, Anne, Cabrini, Alessandro, Torelli, Guido, Maitrejean, Sylvain, Reimbold, Gilles, De Salvo, Barbara, Clermidy, Fabien, Perniola, Luca

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Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2 )/28 nm FDSOI CMOS Technology by Portal, Jean-Michel, Bocquet, Marc, Onkaraiah, Santhosh, Moreau, Mathieu, Aziza, Hassen, Deleruyelle, Damien, Torki, Kholdoun, Vianello, Elisa, Levisse, Alexandre, Giraud, Bastien, Thomas, Olivier, Clermidy, Fabien

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Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications by Melpignano, Diego, Benini, Luca, Flamand, Eric, Jego, Bruno, Lepley, Thierry, Haugou, Germain, Clermidy, Fabien, Dutoit, Denis

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A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip by Lattard, Didier, Beigne, Edith, Bernard, Christian, Bour, Catherine, Clermidy, Fabien, Durand, Yves, Durupt, Jean, Varreau, Didier, Vivet, Pascal, Penard, Pierre, Bouttier, Arnaud, Berens, Friedbert

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A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC by Puschini, Diego, Clermidy, Fabien, Benoit, Pascal, Sassatelli, Gilles, Torres, Lionel

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Designing digital circuits with nano-scale devices: Challenges and opportunities by Belleville, Marc, Thomas, Olivier, Valentian, Alexandre, Clermidy, Fabien

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A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links by Vivet, Pascal, Thonnart, Yvain, Lemaire, Romain, Santos, Cristiano, Beigné, Edith, Bernard, Christian, Darve, Florian, Lattard, Didier, Miro-Panades, Ivan, Dutoit, Denis, Clermidy, Fabien, Chéramy, Séverine, Sheibanyrad, Abbas, Pétrot, Frédéric, Flamand, Eric, Michailos, Jean, Arriordaz, Alexandre, Wang, Lee, Schloeffel, Juergen

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A fully-asynchronous low-power framework for GALS NoC integration by Thonnart, Y, Vivet, P, Clermidy, F

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Fine-Grain Dynamic Energy Tracking for System on Chip by Mansouri, I., Benoit, P., Torres, L., Clermidy, F.

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A 4 \times 4 \times 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links by Vivet, Pascal, Thonnart, Yvain, Lemaire, Romain, Santos, Cristiano, Beigne, Edith, Bernard, Christian, Darve, Florian, Lattard, Didier, Miro-Panades, Ivan, Dutoit, Denis, Clermidy, Fabien, Cheramy, S., Sheibanyrad, Abbas, Petrot, Frederic, Flamand, Eric, Michailos, Jean, Arriordaz, Alexandre, Lee Wang, Schloeffel, Juergen

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RRAM-based FPGA for “Normally Off, Instantly On” applications by Turkyilmaz, Ogun, Onkaraiah, Santhosh, Reyboz, Marina, Clermidy, Fabien, Hraziia, Anghel, Costin, Portal, Jean-Michel, Bocquet, Marc

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MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architectures by Da Rosa, Thiago Raupp, Mesquida, Thomas, Lemaire, Romain, Clermidy, Fabien

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