Hybrid Bonding Technology: Chemical Mechanical Planarization Process Optimization Using Comprehensive 3D Modeling by Jiang, L., Bazizi, E. M., Costrini, G., Lianto, P., See, G., Tsamados, D., Saad, Y., Dag, S., Mehta, G., Yang, Y. C., Sundarrajan, A., Kengeri, S.

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Submicrometer platinum electrodes by through-mask plating by SAENGER, K. L, COSTRINI, G, KOTECKI, D. E, KWIETNIAK, K. T, ANDRICACOS, P. C

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Electromigration in AlCu lines: comparison of Dual Damascene and metal reactive ion etching by Filippi, R.G, Gribelyuk, M.A, Joseph, T, Kane, T, Sullivan, T.D, Clevenger, L.A, Costrini, G, Gambino, J, Iggulden, R.C, Kiewra, E.W, Ning, X.J, Ravikumar, R, Schnabel, R.F, Stojakovic, G, Weber, S.J, Gignac, L.M, Hu, C.-K, Rath, D.L, Rodbell, K.P

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Dual stress liner enhancement in hybrid orientation technology by Sheraw, C.D., Yang, M., Fried, D.M., Costrini, G., Kanarsky, T., Lee, W.-H., Chan, V., Fischetti, M.V., Holt, J., Black, L., Naeem, M., Panda, S., Economikos, L., Groschopf, J., Kapur, A., Li, Y., Mo, R.T., Bonnoit, A., Degraw, D., Luning, S., Chidambarrao, D., Wang, X., Bryant, A., Brown, D., Sung, C.-Y., Agnello, P., Ieong, M., Huang, S.-F., Chen, X., Khare, M.

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Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates by Qiqing Ouyang, Min Yang, Holt, J., Panda, S., Huajie Chen, Utomo, H., Fischetti, M., Rovedo, N., Jinghong Li, Klymko, N., Wildman, H., Kanarsky, T., Costrini, G., Fried, D.M., Bryant, A., Ott, J.A., Meikei Ieong, Chun-Yung Sung

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Aluminum dual damascene metallization for 0.175 μm DRAM generations and beyond ( invited) by Schnabel, R.F, Clevenger, L.A, Costrini, G, Dobuzinsky, D.M, Filippi, R, Gambino, J, Lee, G.Y, Iggulden, R.C, Lin, C, Lu, Z.G, Ning, X.J, Ramachandran, R, Ronay, M, Többen, D, Weber, S.J

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Addressable Arrays Implemented with One Metal Level for MOSFET and Resistor Variability Characterization by Ketchen, M.B., Bhushan, M., Costrini, G.

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22nm technology yield optimization using multivariate 3D virtual fabrication by Cipriany, B., Jagannathan, B., Costrini, G., Noemaun, A., Onishi, K., Narasimha, S., Zhang, B., Sheraw, C., Meiring, J., Kumar, M., Nummy, K., Zhan, N., Nanjundappa, H., Norum, J., Furkay, S., Malik, R., Agnello, P., Fried, D., Greiner, K., Faken, D., Breit, S.

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Conditions for uniform growth of GaAs by metalorganic chemical vapor deposition in a vertical reactor by COSTRINI, G, COLEMAN, J. J

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III-V heterostructure interfaces by metalorganic chemical vapor deposition by COLEMAN, J. J, COSTRINI, G, JENG, S. J, WAYMAN, C. M

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Interface structure of GaAs/AlAs semiconductor superlattices prepared by MOCVD by Jeng, S.J., Wayman, C.M., Costrini, G., Coleman, J.J.

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22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL by Narasimha, S., Chang, P., Ortolland, C., Fried, D., Engbrecht, E., Nummy, K., Parries, P., Ando, T., Aquilino, M., Arnold, N., Bolam, R., Cai, J., Chudzik, M., Cipriany, B., Costrini, G., Dai, M., Dechene, J., DeWan, C., Engel, B., Gribelyuk, M., Guo, D., Han, G., Habib, N., Holt, J., Ioannou, D., Jagannathan, B., Jaeger, D., Johnson, J., Kong, W., Koshy, J., Krishnan, R., Kumar, A., Kumar, M., Lee, J., Li, X., Lin, C., Linder, B., Lucarini, S., Lustig, N., McLaughlin, P., Onishi, K., Ontalus, V., Robison, R., Sheraw, C., Stoker, M., Thomas, A., Wang, G., Wise, R., Zhuang, L., Freeman, G., Gill, J., Maciejewski, E., Malik, R., Norum, J., Agnello, P.

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Three dimensional (BA, SR) TIO 3 stack capacitors for dram application by Nagel, N., Costrini, G., Lian, J., Athavale, S., Economikos, L., Baniecki, J., Wise, M.

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Structural and compositional analyses of GaAs1-xPx/GaAs heterostructures grown by MOCVD by JENG, S. J, WAYMAN, C. M, COSTRINI, G, COLEMAN, J. J

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Stacking and layer disordering of AlxGa1-xAs-GaAs quantum well heterostructures by MEEHAN, K, HSIEH, K. C, COSTRINI, G, KALISKI, R. W, HOLONYAK, N. JR, COLEMAN, J. J

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Growth mechanisms of GaAsP/GaAs heterostructures by metalorganic chemical vapour deposition by Jeng, S.J., Wayman, C.M., Costrini, G., Givens, M.E., Emanuel, M.A., Coleman, J.J.

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Three dimensional (BA, SR) TIO3 stack capacitors for dram application by Nagel, N., Costrini, G., Lian, J., Athavale, S., Economikos, L., Baniecki, J., Wise, M.

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Electrical monitoring of gate and active area mask misalignment error by Bansal, A., Singhee, A., Acar, E., Costrini, G.

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Cleans for Al vias in a 0.175 μm dual damascene process by GAMBINO, J, CLEVENGER, L, BRULEY, J, DOMENICUCCI, A, COSTRINI, G, SCHNABEL, F, RAVIKUMAR, R, DOBUZINSKY, D, IGGULDEN, R, DZIOBKOWSKI, C, WILDMAN, H, BENEDICT, J

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Thermal/electrical behavior of 1 300-nm quad laser arrays in various packaging arrangements by Hoh, P.D., Bates, A.J.S., Strijek, A., Costrini, G., Antreasyan, A., Scontras, S., Ferrario, J., Cahoon, E., Behfar-Rad, A.

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