The flash memory read path: building blocks and critical aspects by Micheloni, R., Crippa, L., Sangalli, M., Campardo, G.

Get full text

A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package by Pulici, P., Girardi, A., Vanalli, G.P., Izzi, R., Bernardi, G., Ripamonti, G., Strollo, A., Campardo, G.

Get full text

A Reduced Output Ringing CMOS Buffer by Bartolini, M., Pulici, P., Stoppino, P.P., Campardo, G., Vanalli, G.P.

Get full text

Special issue on flash memory technology by Campardo, G., Micheloni, R.

Get full text

An overview of flash architectural developments by Campardo, G., Scotti, M., Scommegna, S., Pollara, S., Silvagni, A.

Get full text

Architecture of non volatile memory with multi-bit cells by Campardo, G, Micheloni, R

Get full text

SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era by Maurelli, Alfonso, Belot, Didier, Campardo, Giovanni

Get full text

3-D Integration Technologies [Scanning the Issue] by Campardo, Giovanni, Ripamonti, Giancarlo, Micheloni, Rino

Get full text

Signal Integrity Flow for System-in-Package and Package-on-Package Devices by Pulici, Paolo, Vanalli, Gian Pietro, Dellutri, Michele A., Guarnaccia, Domenico, Lo Iacono, Filippo, Campardo, Giovanni, Ripamonti, Giancarlo

Get full text

40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory by Campardo, G., Micheloni, R., Commodaro, S., Yero, E., Zammattio, M., Mognoni, S., Sacco, A., Picca, M., Manstretta, A., Scotti, M., Motta, I., Golla, C., Pierin, A., Bez, R., Grossi, A., Modelli, A., Visconti, A., Khouri, O., Torelli, G.

Get full text

Hierarchical sector biasing organization for flash memories by Micheloni, R., Zammattio, M., Campardo, G., Khouri, O., Torelli, G.

Request full text

40-mm(2) 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory by Campardo, G, Micheloni, R, Commodaro, S, Yero, E, Zammattio, M, Mognoni, S, Sacco, A, Picca, M, Manstretta, A, Scotti, M, Motta, I, Golla, C, Pierin, A, Bez, R, Grossi, A, Modelli, A, Visconti, A, Khouri, O, Torelli, G

Get full text

Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI by Disegni, F., Annunziata, R., Molgora, A., Campardo, G., Cappelletti, P., Zuliani, P., Ferreira, P., Ventre, A., Castagna, G., Cathelin, A., Gandolfo, A., Goller, F., Malhi, S., Manfre, D., Maurelli, A., Torti, C., Arnaud, F., Carfi, M., Perroni, M., Caruso, M., Pezzini, S., Piazza, G., Weber, O., Peri, M.

Request full text

Program and verify word-line voltage regulator for multilevel Flash memories by Khouri, O, Micheloni, R, Campardo, G, Torelli, G

Get full text

Program word-line voltage generator for multilevel flash memories by Khouri, O., Micheloni, R., Sacco, A., Campardo, G., Torelli, G.

Request full text

40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory by Campardo, G, Micheloni, R, Commodaro, S, Yero, E, Zammattio, M, Mognoni, S, Sacco, A, Picca, M, Manstretta, A, Scotti, M, Motta, I, Golla, C, Pierin, A, Bez, R, Grossi, A, Modelli, A, Visconti, A, Khouri, O, Torelli, G

Get full text

40-mm super(2) 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory by Campardo, G, Micheloni, R, Commodaro, S, Yero, E, Zammattio, M, Mognoni, S, Sacco, A, Picca, M, Manstretta, A, Scotti, M, Motta, I, Golla, C, Pierin, A, Bez, R, Grossi, A, Modelli, A, Visconti, A, Khouri, O, Torelli, G

Get full text

A 40mm super(2) 3V 50MHz 64Mb 4-level cell NOR-type flash memory by Campardo, G, Micheloni, R, Commodaro, S, Yero, E, Zammattio, M, Mognoni, S, Sacco, A, Picca, M, Manstretta, A, Scotti, M, Motta, I, Golla, C, Pierin, A, Ohba, A, Futatsuya, T

Get full text

Risks for Signal Integrity in System in Package and Possible Remedies by Rossi, D., Angelini, P., Metra, C., Campardo, G., Vanalli, G.P.

Request full text

Interconnection effects in Package on Package design by Pulici, P., Candela, G., Campardo, G., Vanalli, G.P., Stoppino, P.P., Losavio, A., Lessio, T., Dellutri, M., Guarnaccia, D., Lo Iacono, F.

Request full text