Search Results - Caramto, R.

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  1. 1
    On the Mechanical Stresses of Cu Through-Silicon Via (TSV) Samples Fabricated by SK Hynix vs. SEMATECH – Enabling Robust and Reliable 3-D Interconnect/Integrated Circuit (IC) Technology

    On the Mechanical Stresses of Cu Through-Silicon Via (TSV) Samples Fabricated by SK Hynix vs. SEMATECH – Enabling Robust and Reliable 3-D Interconnect/Integrated Circuit (IC) Techn... by Tian, Tian, Morusupalli, R., Shin, H., Son, H.-Y., Byun, K.-Y., Joo, Y.-C., Caramto, R., Smith, L., Shen, Y-L., Kunz, M., Tamura, N., Budiman, A.S.

    Published in Procedia engineering
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  2. 2
    300-mm Production-Worthy Magnetically Enhanced Non-Bosch Through-Si-Via Etch for 3-D Logic Integration

    300-mm Production-Worthy Magnetically Enhanced Non-Bosch Through-Si-Via Etch for 3-D Logic Integration by Teh, W H, Caramto, R, Chidambaram, Thenappan, Wei Wang, Arkalgud, Sitaram R, Saito, T, Maruyama, K, Maekawa, Kaoru

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  3. 3
    Mechanical Stress Measurements in Cu Through-Silicon Via (TSV) Using Synchrotron X-Ray Microdiffraction for 3-D Integration

    Mechanical Stress Measurements in Cu Through-Silicon Via (TSV) Using Synchrotron X-Ray Microdiffraction for 3-D Integration by Budiman, Arief, Shin, H A-S, Kim, B-J, Hwang, S-H, Son, H-Y, Suh, M-S, Chung, Q-H, Byun, K-Y, Joo, Y-C, Caramto, R, Smith, L, Kunz, M, Tamura, N

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  4. 4
    On the technology and ecosystem of 3D / TSV manufacturing

    On the technology and ecosystem of 3D / TSV manufacturing by Hummler, K., Smith, L., Caramto, R., Edgeworth, R., Olson, S., Pascual, D., Qureshi, J., Rudack, A., Quon, R., Arkalgud, S.

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  5. 5
    Thermal and spatial dependence of TSV-induced stress in Si

    Thermal and spatial dependence of TSV-induced stress in Si by McDonough, C., Backes, B., Wang, W., Caramto, R., Geer, R. E.

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  6. 6
    Magnetically-enhanced capacitively-coupled plasma etching for 300 mm wafer-scale fabrication of Cu through-silicon-vias for 3D logic integration

    Magnetically-enhanced capacitively-coupled plasma etching for 300 mm wafer-scale fabrication of Cu through-silicon-vias for 3D logic integration by Teh, W.H., Caramto, R., Arkalgud, S., Saito, T., Maruyama, K., Maekawa, K.

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  7. 7
    Comparison of mechanical stresses of Cu Through-Silicon Via (TSV) samples fabricated by Hynix vs. SEMATECH using synchrotron X-ray microdiffraction for 3-D integration and reliability

    Comparison of mechanical stresses of Cu Through-Silicon Via (TSV) samples fabricated by Hynix vs. SEMATECH using synchrotron X-ray microdiffraction for 3-D integration and reliabil... by Budiman, A. S., Shin, H., Kim, B.-J, Hwang, S.-H, Son, H.-Y, Suh, M.-S, Chung, Q.-H, Byun, K.-Y, Joo, Y.-C, Caramto, R., Smith, L., Kunz, M., Tamura, N.

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  8. 8
    A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration

    A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration by Teh, W.H., Caramto, R., Qureshi, J., Arkalgud, S., O'Brien, M., Gilday, T., Maekawa, K., Saito, T., Maruyama, K., Chidambaram, T., Wang, W., Marx, D., Grant, D., Dudley, R.

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