Search Results - Chang, Tien-Tang

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  1. 1
    Using Sidereal Rotation Period Expressions to Calculate the Sun’s Rotation Period through Observation of Sunspots

    Using Sidereal Rotation Period Expressions to Calculate the Sun’s Rotation Period through Observation of Sunspots by Ho, Ming-Chung, Lu, Ming-Chi, Yang, Chih-Hung, Chang, Tien-Tang, Lih, Jiann-Shing, Chen, Tsung-Ching, Liu, Chia-Ju

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  2. 2
    Corrigendum to “Using Sidereal Rotation Period Expressions to Calculate the Sun’s Rotation Period through Observation of Sunspots”

    Corrigendum to “Using Sidereal Rotation Period Expressions to Calculate the Sun’s Rotation Period through Observation of Sunspots” by Ho, Ming-Chung, Lu, Ming-Chi, Yang, Chih-Hung, Chang, Tien-Tang, Lih, Jiann-Shing, Chen, Tsung-Ching, Liu, Chia-Ju

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  3. 3
    Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

    Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET by Chun Chiang, Ping-Chen Chang, Pei-Shan Tseng, Po-Ya Lai, Tien-Hao Tang, Kuan-Cheng Su

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  4. 4
    ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

    ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process by Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang, Kuan-Cheng Su

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  5. 5
    Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

    Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology by Chang-Tzu Wang, Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su

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  6. 6
    Latch-up free ESD protection design with SCR structure in advanced CMOS technology

    Latch-up free ESD protection design with SCR structure in advanced CMOS technology by Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su

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  7. 7
    High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

    High-robust ESD protection structure with embedded SCR in high-voltage CMOS process by Tai-Hsiang Lai, Ming-Dou Ker, Wei-Jen Chang, Tien-Hao Tang, Kuan-Cheng Su

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  8. 8
    Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

    Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes by Ming-Dou Ker, Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su

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  9. 9
    Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process

    Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process by Shiao-Shien Chen, Tung-Yang Chen, Tien-Hao Tang, Shao-Chang Huang, Hsu, T.-L., Hua-Chou Tseng, Jen-Kon Chen, Chiu-Hsiang Chou

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  10. 10
    Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

    Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering by Chiang, Chun, Chang, Ping-Chen, Chao, Mei-Ling, Tang, Tien-Hao, Su, Kuan-Cheng, Ker, Ming-Dou

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  11. 11
    The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

    The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications by Lu-An Chen, Chang-Tzu Wang, Tai-Hsiang Lai, Tien-Hao Tang, Kuan-Cheng Su

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  12. 12
    Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application

    Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application by Chiang, Chun, Chang, Ping-Chen, Tang, Tien-Hao, Su, Kuan-Cheng

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  13. 13
    ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

    ESD Robustness of 40-V CMOS Devices With/Without Drift Implant by Wei-Jen Chang, Ming-Dou Ker, Tai-Hsiang Lai, Tien-Hao Tang, Kuan-Cheng Su

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  14. 14
    The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process

    The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process by Wei-Jen Chang, Ming-Dou Ker, Tai-Xiang Lai, Tien-Hao Tang, Kuan-Cheng Su

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  15. 15
    ESD protection design with lateral DMOS transistor in 40-V BCD technology

    ESD protection design with lateral DMOS transistor in 40-V BCD technology by Chang-Tzu Wang, Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su

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  16. 16
    Image-based detection and obstacle avoidance for mobile robots

    Image-based detection and obstacle avoidance for mobile robots by Cheng-Chuan Chen, Ming-Chih Lu, Pei-Chun Chang, Cheng-Pei Tsai, Tien-Yu Tang

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  17. 17
    Investigation of a SiGe HBT during ESD stress in a 0.18-[micro]m SiGe BiCMOS process

    Investigation of a SiGe HBT during ESD stress in a 0.18-[micro]m SiGe BiCMOS process by Chen, Shiao-Shien, Chen, Tung-Yang, Tang, Tien-Hao, Huang, Shao-Chang, Hsu, T.-L, Tseng, Hua-Chou, Chen, Jen-Kon, Chou, Chiu-Hsiang

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  18. 18
    Investigation of a SiGe HBT during ESD stress in a 0.18-mum SiGe BiCMOS process

    Investigation of a SiGe HBT during ESD stress in a 0.18-mum SiGe BiCMOS process by Chen, Shiao-Shien, Chen, Tung-Yang, Tang, Tien-Hao, Huang, Shao-Chang, Hsu, T-L, Tseng, Hua-Chou, Chen, Jen-Kon, Chou, Chiu-Hsiang

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  19. 19
    Investigation of a SiGe HBT during ESD stress in a 0.18-micron SiGe BiCMOS process

    Investigation of a SiGe HBT during ESD stress in a 0.18-micron SiGe BiCMOS process by Chen, Shiao-Shien, Chen, Tung-Yang, Tang, Tien-Hao, Huang, Shao-Chang, Hsu, T.-L., Tseng, Hua-Chou, Chen, Jen-Kon, Chou, Chiu-Hsiang

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