Search Results - Chishti, Zeshan

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  1. 1
    DRAM Refresh Mechanisms, Penalties, and Trade-Offs

    DRAM Refresh Mechanisms, Penalties, and Trade-Offs by Bhati, Ishwar, Mu-Tien Chang, Chishti, Zeshan, Shih-Lien Lu, Jacob, Bruce

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  2. 2
    TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems

    TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems by Young, Vinson, Chishti, Zeshan A., Qureshi, Moinuddin K.

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  3. 3
    Transparent Hardware Management of Stacked DRAM as Part of Memory

    Transparent Hardware Management of Stacked DRAM as Part of Memory by Jaewoong Sim, Alameldeen, Alaa R., Chishti, Zeshan, Wilkerson, Chris, Hyesoon Kim

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  4. 4
    Improving cache lifetime reliability at ultra-low voltages

    Improving cache lifetime reliability at ultra-low voltages by Chishti, Zeshan, Alameldeen, Alaa R., Wilkerson, Chris, Wu, Wei, Lu, Shih-Lien

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  5. 5
    Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

    Trading off Cache Capacity for Reliability to Enable Low Voltage Operation by Wilkerson, Chris, Gao, Hongliang, Alameldeen, Alaa R., Chishti, Zeshan, Khellah, Muhammad, Lu, Shih-Lien

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  6. 6
    Improving DRAM performance by parallelizing refreshes with accesses

    Improving DRAM performance by parallelizing refreshes with accesses by Chang, Kevin Kai-Wei, Donghyuk Lee, Chishti, Zeshan, Alameldeen, Alaa R., Wilkerson, Chris, Yoongu Kim, Mutlu, Onur

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  7. 7
    Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions

    Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions by Bhati, Ishwar, Chishti, Zeshan, Shih-Lien Lu, Jacob, Bruce

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  8. 8
    Optimizing Replication, Communication, and Capacity Allocation in CMPs

    Optimizing Replication, Communication, and Capacity Allocation in CMPs by Chishti, Zeshan, Powell, Michael D., Vijaykumar, T. N.

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  9. 9
    Rank-aware cache replacement and write buffering to improve DRAM energy efficiency

    Rank-aware cache replacement and write buffering to improve DRAM energy efficiency by Amin, Ahmed M., Chishti, Zeshan A.

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  10. 10
    Operating SECDED-based caches at ultra-low voltage with FLAIR

    Operating SECDED-based caches at ultra-low voltage with FLAIR by Qureshi, Moinuddin K., Chishti, Zeshan

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  11. 11
    Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

    Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling by Bhati, Ishwar, Chishti, Zeshan, Jacob, Bruce

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  12. 12
    Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling

    Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling by Kotra, Jagadish B., Shahidi, Narges, Chishti, Zeshan A., Kandemir, Mahmut T.

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  13. 13
    Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers

    Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers by Pugsley, Seth H., Chishti, Zeshan, Wilkerson, Chris, Peng-fei Chuang, Scott, Robert L., Jaleel, Aamer, Shih-Lien Lu, Chow, Kingsum, Balasubramonian, Rajeev

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  14. 14
    Energy-efficient cache design using variable-strength error-correcting codes

    Energy-efficient cache design using variable-strength error-correcting codes by Alameldeen, Alaa R., Wagner, Ilya, Chishti, Zeshan, Wu, Wei, Wilkerson, Chris, Lu, Shih-Lien

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  15. 15
    Adaptive Cache Design to Enable Reliable Low-Voltage Operation

    Adaptive Cache Design to Enable Reliable Low-Voltage Operation by Alameldeen, A R, Chishti, Z, Wilkerson, C, Wei Wu, Shih-Lien Lu

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  16. 16
    Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

    Trading off Cache Capacity for Reliability to Enable Low Voltage Operation by Wilkerson, Chris, Gao, Hongliang, Alameldeen, Alaa R., Chishti, Zeshan, Khellah, Muhammad, Lu, Shih-Lien

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  17. 17
    Coordinated refresh: energy efficient techniques for DRAM refresh scheduling

    Coordinated refresh: energy efficient techniques for DRAM refresh scheduling by Bhati, Ishwar, Chishti, Zeshan, Jacob, Bruce

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  18. 18
    Architectural Support for Efficient Data Movement in Fully Disaggregated Systems

    Architectural Support for Efficient Data Movement in Fully Disaggregated Systems by Giannoula, Christina, Huang, Kailong, Tang, Jonathan, Koziris, Nectarios, Goumas, Georgios, Chishti, Zeshan, Vijaykumar, Nandita

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  19. 19
    Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies

    Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies by Chishti, Z., Vijaykumar, T.N.

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  20. 20
    Optimizing Replication, Communication, and Capacity Allocation in CMPs

    Optimizing Replication, Communication, and Capacity Allocation in CMPs by Chishti, Zeshan, Powell, Michael D., Vijaykumar, T. N.

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