Search Results - Chiu, Jih-Ching

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  1. 1
    Design and Implementation of Nursing-Secure-Care System with mmWave Radar by YOLO-v4 Computing Methods

    Design and Implementation of Nursing-Secure-Care System with mmWave Radar by YOLO-v4 Computing Methods by Chiu, Jih-Ching, Lee, Guan-Yi, Hsieh, Chih-Yang, Lin, Qing-You

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  2. 2
    Communication Performance Assessment for Advanced Metering Infrastructure

    Communication Performance Assessment for Advanced Metering Infrastructure by Teng, Jen-Hao, Chao, Chia-Wei, Liu, Bin-Han, Huang, Wei-Hao, Chiu, Jih-Ching

    Published in Energies (Basel)
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  3. 3
    Two-Dimensional Interpolation-Assisted Channel Prediction for OFDM Systems

    Two-Dimensional Interpolation-Assisted Channel Prediction for OFDM Systems by LEE, Hsuan-Chang, CHIU, Jih-Ching, LIN, Ken-Huang

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  4. 4
    High-speed low-power multiplexer-based selector for priority policy

    High-speed low-power multiplexer-based selector for priority policy by Chiu, Jih-ching, Yang, Kai-ming

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  5. 5
    A hyperscalar dual-core architecture for embedded systems

    A hyperscalar dual-core architecture for embedded systems by Chiu, Jih-Ching, Yang, Kai-Ming, Chou, Yu-Liang

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  6. 6
    The Rendezvous Mechanism for the Multi-core AMBA System

    The Rendezvous Mechanism for the Multi-core AMBA System by Jih-Ching Chiu, Kai-Ming Yang, Mu-Chi Chang

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  7. 7
    A relation-exchanging buffering mechanism for instruction and data streaming

    A relation-exchanging buffering mechanism for instruction and data streaming by Chiu, Jih-Ching, Yang, Kai-Ming, Chou, Yu-Liang, Wu, Chih-Kang

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  8. 8
    A Novel instruction stream buffer for VLIW architectures

    A Novel instruction stream buffer for VLIW architectures by Chiu, Jih-Ching, Yang, Kai-Ming

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  9. 9
    A multi-streaming SIMD multimedia computing engine

    A multi-streaming SIMD multimedia computing engine by Chiu, Jih-Ching, Chou, Yu-Liang

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  10. 10
    A Unitable Computing Architecture for Chip Multiprocessors

    A Unitable Computing Architecture for Chip Multiprocessors by Chiu, Jih-Ching, Chou, Yu-Liang, Chen, Po-Kai, Su, Ding-Siang

    Published in Computer journal
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  11. 11
    Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture

    Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture by Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen

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  12. 12
    The DDRx memory controller extended for reconfigurable computing

    The DDRx memory controller extended for reconfigurable computing by Jih-Ching Chiu, Kai-Ming Yang

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  13. 13
    Variable-size data item placement for load and storage balancing

    Variable-size data item placement for load and storage balancing by Ma, Yung-Cheng, Chiu, Jih-Ching, Chen, Tien-Fu, Chung, Chung-Ping

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  14. 14
    Design of an asynchronous ring bus architecture for multi-core systems

    Design of an asynchronous ring bus architecture for multi-core systems by Kai-ming Yang, Kin-fong Lei, Jih-ching Chiu

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  15. 15
    A hardware invocation mechanism for reconfigurable embedded system

    A hardware invocation mechanism for reconfigurable embedded system by Jih-Ching Chiu, Kai-Ming Yang, Ta-Li Yeh

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  16. 16
    Implementation of action recognition algorithm on multiple-streaming multimedia unit

    Implementation of action recognition algorithm on multiple-streaming multimedia unit by Jih-ching Chiu, Tzu-Chun Lin, Yu-Liang Chou

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  17. 17
    The Software and Hardware Integration Linker for Reconfigurable Embedded System

    The Software and Hardware Integration Linker for Reconfigurable Embedded System by Jih-Ching Chiu, Ta-Li Yeh, Mun-Kit Leong

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  18. 18
    Dynamic Multi-channel Multi-path Routing Protocol for wireless mesh networks

    Dynamic Multi-channel Multi-path Routing Protocol for wireless mesh networks by Kai-ming Yang, Ming-Shiou Wu, Po-Hsun Pan, Jih-ching Chiu

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  19. 19
    Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA

    Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA by Jih Ching Chiu, Yu Liang Chou, Ta Li Yeh, Tseng Kuei Lin

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  20. 20
    Design of instruction stream buffer with trace support for X86 processors

    Design of instruction stream buffer with trace support for X86 processors by Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung

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