Search Results - Choul-Joo Ko

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  1. 1
    Implementation of fully isolated Low Vgs nLDMOS with low specific on-resistance

    Implementation of fully isolated Low Vgs nLDMOS with low specific on-resistance by Choul-Joo Ko, Cheol-Ho Cho, Min-Seok Kim, Hyung-Gyun Jung, Hee-Bae Lee, Yong-Jun Lee, Min-Woo Kim, Sung-Mo Gu, Sun-Kyung Bang, Han-Geon Kim, Sun-Kyoung Kang, Kwang-Dong Yoo, Hutter, L.

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  2. 2
    Implementation of 85V High Side LDMOS with n-layer in a 0.35um BCD Process

    Implementation of 85V High Side LDMOS with n-layer in a 0.35um BCD Process by Choul-Joo Ko, Sang-Yong Lee, Il-Yong Park, Cho-Eung Park, Bon-Keun Jun, Yong-Jun Lee, Chan-Hee Kang, Jae-O Lee, Nam-Joo Kim, Kwang-Dong Yoo

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  3. 3
    Low Vgs P-ch LDMOS with Sallow Pwell from 8V to 60V

    Low Vgs P-ch LDMOS with Sallow Pwell from 8V to 60V by Choul-Joo Ko, Cheol-Ho Cho, Hee-Bae Lee, Yong-Jun Lee, Min-Woo Kim, Sun-Kyung Bang, Han-Geon Kim, Sang-Chul Shim, Sun Kyoung Kang, Nam-Joo Kim, Kwang-Dong Yoo, Hutter, L N

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  4. 4
    A new 8V - 60V rated low Vgs NLDMOS structure with enhanced specific on-resistance

    A new 8V - 60V rated low Vgs NLDMOS structure with enhanced specific on-resistance by Choul-Joo Ko, Cheol-Ho Cho, Hee-Bae Lee, Yong-Jun Lee, Min-Woo Kim, Sun-Kyung Bang, Han-Geon Kim, Jae-O Lee, Sang-Chul Shim, Sun Kyoung Kang, Nam-Joo Kim, Kwang-Dong Yoo, Hutter, L N

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  5. 5
    Process-induced charge trapping and junction breakdown instability in deep trench isolation for high voltage Smart Power IC process

    Process-induced charge trapping and junction breakdown instability in deep trench isolation for high voltage Smart Power IC process by Hee-dae Kim, Ju-won Park, Choul-Joo Ko, Bon-Keun Jun, Namchil Moon, KyungWook Kwon, Changjun Lee, Kunsik Sung, Nam-Joo Kim, Kwang-Dong Yoo, Yoon-Jong Lee

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