Search Results - Chuck Yuan

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  1. 1
    A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver

    A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver by Kaviani, K., Amirkhany, A., Huang, C., Phuong Le, Beyene, W. T., Madden, C., Saito, K., Sano, K., Murugan, V. I., Kun-Yung Ken Chang, Yuan, X. C.

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  2. 2
    Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

    Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs by Kyung Suk Oh, Lambrecht, F., Sam Chang, Qi Lin, Jihong Ren, Chuck Yuan, Zerbe, J., Stojanovic, V.

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  3. 3
    A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link

    A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link by Amirkhany, A., Kaviani, K., Abbasfar, A., Fazeel, S., Beyene, W., Hoshino, C., Madden, C., Chang, K., Yuan, C.

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  4. 4
    Frequency-domain figures-of-merit for the design of interface supply networks

    Frequency-domain figures-of-merit for the design of interface supply networks by Schmitt, R., Joong-Ho Kim, Chuck Yuan

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  5. 5
    Investigating the Impact of Supply Noise on the Jitter in Gigabit I/O Interfaces

    Investigating the Impact of Supply Noise on the Jitter in Gigabit I/O Interfaces by Schmitt, R., Hai Lan, Madden, C., Chuck Yuan

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  6. 6
    Jitter Amplification Considerations for PCB Clock Channel Design

    Jitter Amplification Considerations for PCB Clock Channel Design by Madden, C., Sam Chang, Dan Oh, Chuck Yuan

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  7. 7
    A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration

    A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration by Kaviani, K., Amirkhany, A., Huang, C., Le, P., Madden, C., Saito, K., Sano, K., Murugan, V., Beyene, W., Chang, K., Yuan, C.

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  8. 8
    Investigating substrate coupling noise impact on low-power memory controller PHY interface using on-chip measurement structure

    Investigating substrate coupling noise impact on low-power memory controller PHY interface using on-chip measurement structure by Hai Lan, Aleksic, M, Schmitt, R, Nhat Nguyen, Chuck Yuan

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  9. 9
    Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces

    Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces by Hai Lan, Schmitt, R., Chuck Yuan

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  10. 10
    Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

    Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems by Joong-Ho Kim, Woopoung Kim, Oh, D., Schmitt, R., Feng, J., Chuck Yuan, Luo, L., Wilson, J.

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  11. 11
    A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link

    A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link by Amirkhany, A., Kaviani, K., Abbasfar, A., Shuaeb, F., Beyene, W., Hoshino, C., Madden, C., Ken Chang, Yuan, C.

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  12. 12
    Prediction of System Performance Based on Component Jitter and Noise Budgets

    Prediction of System Performance Based on Component Jitter and Noise Budgets by Dan Oh, Lambrecht, F., JiHong Ren, Sam Chang, Ben Chia, Madden, C., Chuck Yuan

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  13. 13
    Challenges and solutions for next generation main memory systems

    Challenges and solutions for next generation main memory systems by Joong-Ho Kim, Dan Oh, Kollipara, R., Wilson, J., Best, S., Giovannini, T., Shaeffer, I., Ching, M., Chuck Yuan

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  14. 14
    Study of PCB Trace Crosstalk in Backplane Connector Pin Field

    Study of PCB Trace Crosstalk in Backplane Connector Pin Field by Chia, B., Kollipara, R., Oh, D., Yuan, C., Boluna, L.S.

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  15. 15
    Evaluation of high density liquid crystal polymer based flex interconnect for supporting greater than 1 TB/s of memory bandwidth

    Evaluation of high density liquid crystal polymer based flex interconnect for supporting greater than 1 TB/s of memory bandwidth by Kollipara, R., Ming Li, Chuck Yuan, Kusamitsu, H., Ito, T.

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  16. 16
    S-parameters Based Transmission Line Modeling with Accurate Low-Frequency Response

    S-parameters Based Transmission Line Modeling with Accurate Low-Frequency Response by WooPoung Kim, Joong-Ho Kim, Dan Oh, Chuck Yuan

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  17. 17
    Design and testing of a high speed module based memory system

    Design and testing of a high speed module based memory system by Kollipara, R., Ming Li, Mullen, D., Beyene, W., Madden, C., Chuck Yuan, Kusamitsu, H., Ito, T.

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  18. 18
    Compact on-chip wire models for the clock distribution of high-speed I/O interfaces

    Compact on-chip wire models for the clock distribution of high-speed I/O interfaces by Xiaoning Qi, Joong-Ho Kim, Ling Yang, Schmitt, R., Chuck Yuan

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  19. 19
    An accurate transient analysis of high-speed package interconnects using convolution technique

    An accurate transient analysis of high-speed package interconnects using convolution technique by Beyene, W T, Yuan, C

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  20. 20
    Accurate System Voltage and Timing Margin Simulation in CDR Based High Speed Designs

    Accurate System Voltage and Timing Margin Simulation in CDR Based High Speed Designs by Lambrecht, F., Qi Lin, Sam Chang, Dan Oh, Chuck Yuan, Stojanovic, V.

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