Modeling Advanced FET Technology in a Compact Model by Dunga, M.V., Chung-Hsun Lin, Xuemei Xi, Lu, D.D., Niknejad, A.M., Chenming Hu

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Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors by Cheema, Suraj S., Shanker, Nirmaan, Wang, Li-Chen, Hsu, Cheng-Hsiang, Hsu, Shang-Lin, Liao, Yu-Hung, San Jose, Matthew, Gomez, Jorge, Chakraborty, Wriddhi, Li, Wenshen, Bae, Jong-Ho, Volkman, Steve K., Kwon, Daewoong, Rho, Yoonsoo, Pinelli, Gianni, Rastogi, Ravi, Pipitone, Dominick, Stull, Corey, Cook, Matthew, Tyrrell, Brian, Stoica, Vladimir A., Zhang, Zhan, Freeland, John W., Tassone, Christopher J., Mehta, Apurva, Saheli, Ghazal, Thompson, David, Suh, Dong Ik, Koo, Won-Tae, Nam, Kab-Jin, Jung, Dong Jin, Song, Woo-Bin, Lin, Chung-Hsun, Nam, Seunggeol, Heo, Jinseong, Parihar, Narendra, Grigoropoulos, Costas P., Shafer, Padraic, Fay, Patrick, Ramesh, Ramamoorthy, Mahapatra, Souvik, Ciston, Jim, Datta, Suman, Mohamed, Mohamed, Hu, Chenming, Salahuddin, Sayeef

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Performance-Aware Corner Model for Design for Manufacturing by Chung-Hsun Lin, Dunga, M.V., Lu, D.D., Niknejad, A.M., Chenming Hu

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Extraction of Effective Oxide Thickness for SOI FINFETs With High- \kappa/Metal Gates Using the Body Effect by Paul, Sujata, Yeh, Frank, Maitra, Kingsuk, Chung-Hsun Lin, Kerber, Andreas, Kulkarni, Pranita, Jagannathan, Hemanth, Basker, Veeraraghavan S, Miller, Robert J, Huiming Bu

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Gate capacitance of cylindrical nanowires with elliptical cross-sections by Majumdar, Amlan, Lin, Chung-Hsun

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Combining Expression Data and Knowledge Ontology for Gene Clustering and Network Reconstruction by Lee, Wei-Po, Lin, Chung-Hsun

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Non-planar device architecture for 15nm node: FinFET or trigate? by Chung-Hsun Lin, Chang, J, Guillorn, M, Bryant, A, Oldiges, P, Haensch, W

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BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design by Dunga, M.V., Chung-Hsun Lin, Lu, D.D., Weize Xiong, Cleavelin, C.R., Patruno, P., Jiunn-Ren Hwang, Fu-Liang Yang, Niknejad, A.M., Chenming Hu

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A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates by Lu, Darsen D., Dunga, Mohan V., Lin, Chung-Hsun, Niknejad, Ali M., Hu, Chenming

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Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs by Chan, Mansun, Su, Pin, Wan, Hui, Lin, Chung-Hsun, Fung, Samuel K.-H., Niknejad, Ali M., Hu, Chenming, Ko, Ping K.

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Patterning nanowire and micro-/nanoparticle array on micropillar-structured surface: Experiment and modeling by Lin, Chung Hsun, Guan, Jingjiao, Chau, Shiu Wu, Chen, Shia Chung, Lee, L. James

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HOT-carrier degradation in undoped-body ETSOI FETS and SOI FINFETS by Miaomiao Wang, Kulkarni, Pranita, Kangguo Cheng, Khakifirooz, Ali, Basker, V S, Jagannathan, Hemanth, Chun-Chen Yeh, Paruchuri, Vamsi, Doris, Bruce, Huiming Bu, Chung-Hsun Lin, Stathis, James H, Maitra, Kingsuk, Oldiges, Philip J

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A comparative study of fin-last and fin-first SOI FinFETs by Lu, Darsen, Chang, Josephine, Guillorn, Michael A., Chung-Hsun Lin, Johnson, Jeffrey, Oldiges, Philip, Rim, Ken, Khare, Mukesh, Haensch, Wilfried

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Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond by Chung-Hsun Lin, Haensch, W., Oldiges, P., Hailing Wang, Williams, R., Chang, J., Guillorn, M., Bryant, A., Yamashita, T., Standaert, T., Bu, H., Leobandung, E., Khare, M.

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Scaffold design considerations for peripheral nerve regeneration by Yu, Le, Bennett, Carly Jane, Lin, Chung-Hsun, Yan, Su, Yang, Jian

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Design of FinFET SRAM Cells Using a Statistical Compact Model by Lu, D.D., Chung-Hsun Lin, Shijing Yao, Weize Xiong, Bauer, F., Cleavelin, C.R., Niknejad, A.M., Chenming Hu

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Compact Modeling of Variation in FinFET SRAM Cells by Lu, D.D., Chung-Hsun Lin, Niknejad, A.M., Chenming Hu

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Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility by Ruqiang Bao, Greene, Brian, Unoh Kwon, Sungjae Lee, Bruley, John, Weike Wang, Kai Zhao, DeHaven, Patrick W., Zhengwen Li, Wong, Keith, Grunow, Stephan, Divakaruni, Rama, Chung-Hsun Lin, Krishnan, Siddarth A., Narayanan, Vijay

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A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation by Lu, D.D., Dunga, M.V., Chung-Hsun Lin, Niknejad, A.M., Chenming Hu

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FinFET resistance mitigation through design and process optimization by Wang, C., Chang, J., Chung-Hsun Lin, Kumar, A., Gehring, A., Jin Cho, Majumdar, A., Bryant, A., Zhibin Ren, Chan, K., Kanarsky, T., Xinlin Wang, Dokumaci, O., Guillorn, M., Khater, M., Qingyun Yang, Xi Li, Naeem, M., Holt, J., Yongsik Moon, King, J., Yates, J., Ying Zhang, Dae-gyu Park, Ouyang, C., Haensch, W.

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