Reduced electron mobility due to nitrogen implant prior to the gate oxide growth by Kamgar, A., Clemens, J.T., Ghetti, A., Liu, C.T., Lloyd, E.J.

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Merged DRAM-logic in the year 2001 by Diodato, P.W., Noda, L., Wong, Y.-H., Drynan, J.M., Liu, C.-T., Lee, K.-H., Dail, R., Lindenberger, W.S., Dumbri, A.C., Depaolis, M.V., Clemens, J.T., Troutman, W.W., Nakamae, M.

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Limitation of post-metallization annealing due to hydrogen blocking effect of multilevel interconnect by Ito, S., Noguchi, K., Horiuchi, T., Clemens, J.T.

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Field dependent critical trap density for thin gate oxide breakdown by Cheung, K.P., Liu, C.T., Chang, C.-P., Colonell, J.I., Lai, W.Y.-C., Liu, R., Miner, J.F., Pai, C.S., Vaidya, H., Clemens, J.T., Hasegawa, E.

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A new mode of hot carrier degradation in 0.18 /spl mu/m CMOS technologies by Liu, C.T., Lloyd, E.J., Chang, C.P., Cheung, K.P., Colonell, J.I., Lai, W.Y.C., Liu, R., Pai, C.S., Vaidya, H., Clemens, J.T.

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A reusable embedded DRAM macrocell by Diodato, P.W., Clemens, J.T., Troutman, W.W., Lindenberger, W.S.

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Impact of nitrogen implant prior to the gate oxide growth on transient enhanced diffusion by Kamgar, A., Vuong, H.-H., Liu, C.T., Rafferty, C.S., Clemens, J.T.

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A model of the stress time dependence of SILC by Lu, Q., Cheung, K.P., Ciampa, N.A., Liu, C.T., Chang, C.-P., Colonell, J.I., Lai, W.-Y.-C., Liu, R., Miner, J.F., Vaidya, H., Pai, C.-S., Clemens, J.T.

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Reduced 1/f noise and g/sub m/ degradation for sub-0.25 /spl mu/m MOSFETs with 25 /spl Aring/-50 /spl Aring/ gate oxides grown on nitrogen implanted Si substrates by Liu, C.T., Misra, D., Cheung, K.P., Alers, G.B., Chang, C.P., Colonell, J.I., Lai, W.Y.C., Pai, C.S., Liu, R., Clemens, J.T.

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Charging damage in thin gate-oxides-better or worse? by Cheung, K.P., Liu, C.-T., Chang, C.-P., Colonell, J.I., Lai, W.-Y.-C., Pai, C.-S., Vaidya, H., Liu, R., Clemens, J.T., Hasegawa, E.

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Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress by Liu, C.T., Baumann, F.H., Ghetti, A., Vuong, H.H., Chang, C.P., Cheung, K.P., Colonell, J.I., Lai, W.Y.C., Lloyd, E.J., Miner, J.F., Pai, C.S., Vaidya, H., Liu, R., Clemens, J.T.

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Relationship between plasma damage, SILC and gate-oxide reliability by Cheung, K.P., Lu, Q., Ciampa, N.A., Liu, C.T., Chang, C.-P., Colonell, J.I., Lai, W.-Y.-C., Liu, R., Miner, J.F., Vaidya, H., Pai, C.-S., Clemens, J.T.

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Gate-oxide degradation from source/drain (S/D) boron diffusion by Cheung, K.P., Chang, C.-P., Colonell, J.I., Lai, W.-Y.-C., Liu, C.-T., Liu, R., Pai, C.-S., Rafferty, C.S., Vaidya, H., Clemens, J.T.

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Is surface potential measurement (SPM) a useful charging damage measurement method? by Cheung, K.P., Colonell, J.I., Steiner, K.G., Shive, S., Kook, T., Chang, C.-P., Lai, W.-Y.-C., Liu, C.-T., Liu, R., Pai, C.-S., Vaidya, H., Clemens, J.T.

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Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxides by Liu, C.T., Ghetti, A., Ma, Y., Alers, G., Chang, C.P., Cheung, K.P., Colonell, J.I., Lai, W.Y.C., Pai, C.S., Liu, R., Vaidya, H., Clemens, J.T.

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Enabling shallow trench isolation for 0.1 /spl mu/m technologies and beyond by Chang, C.-P., Shive, S.F., Kuehne, S.C., Ma, Y., Vuong, H., Baumann, F.H., Bude, M., Lloyd, E.J., Pai, C.S., Abdelgadir, M.A., Dail, R., Liu, C.T., Cheung, K.P., Colonell, J.I., Lai, W.Y.C., Miner, J.F., Vaidya, H., Liu, R.C., Clemens, J.T.

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A manufacturable embedded fluorinated SiO/sub 2/ for advanced 0.25 /spl mu/m CMOS VLSI multilevel interconnect applications by Pai, C.S., Velaga, A.N., Lindenberger, W.S., Lai, W.Y.-C., Cheung, K.P., Baumann, F.H., Chang, C.P., Liu, C.T., Liu, R., Diodato, P.W., Colonell, J.I., Vaidya, H., Vitkavage, S.C., Clemens, J.T., Tsubokura, F.

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A highly manufacturable corner rounding solution for 0.18 /spl mu/m shallow trench isolation by Chang, C.P., Pai, C.S., Baumann, F.H., Liu, C.T., Rafferty, C.S., Pinto, M.R., Lloyd, E.J., Bude, M., Klemens, F.P., Miner, J.F., Cheung, K.P., Colonell, J.I., Lai, W.Y.C., Vaidya, H., Hillenius, S.J., Liu, R.C., Clemens, J.T.

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Multiple gate oxide thickness for 2 GHz system-on-a-chip technologies by Liu, C.T., Ma, Y., Oh, M., Diodato, P.W., Stiles, K.R., Mcmacken, J.R., Li, F., Chang, C.P., Cheung, K.P., Colonell, J.I., Lai, W.Y.C., Liu, R., Lloyd, E.J., Miner, J.F., Pai, C.S., Vaidya, H., Frackoviak, J., Timko, A., Klemens, F., Maynard, H., Clemens, J.T.

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Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology by Bevk, J., Kuehne, S., Vaidya, H., Mansfield, W., Hobler, G., Boulin, D.M., Bolan, K., Chang, C.P., Cheung, K.P., Cirelli, R., Colonell, J.I., Frackoviak, J., Frei, M., Gruensfelder, C., Jacobson, D.C., Key, R.W., Klemens, F.P., Lai, W.Y.C., Lee, J.T.-C., Liu, C.T., Liu, R., Oh, M., Maynard, H.L., Monroe, D.P., Nalamasu, O., Pai, C.S., Santiesteban, R., Silverman, P.J., Tai, W.W., Timko, A., Vuong, H., Watson, G.P., Thoma, M.J., Clemens, J.T., Hillenius, S.J.

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