Search Results - Codinachs, David Merodio

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  1. 1
    Ultrahigh Energy Heavy Ion Test Beam on Xilinx Kintex-7 SRAM-Based FPGA

    Ultrahigh Energy Heavy Ion Test Beam on Xilinx Kintex-7 SRAM-Based FPGA by Du, Boyang, Sterpone, Luca, Azimi, Sarah, Merodio Codinachs, David, Ferlet-Cavrois, Veronique, Boatella Polo, Cesar, Alia, Ruben Garcia, Kastriotou, Maria, Fernandez-Martinez, Pablo

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  2. 2
    Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems

    Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems by Azimi, Sarah, De Sio, Corrado, Portaluri, Andrea, Rizzieri, Daniele, Vacca, Eleonora, Sterpone, Luca, Merodio Codinachs, David

    Published in Electronics (Basel)
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  3. 3
    Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks

    Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks by Leon, Vasileios, Stamoulias, Ioannis, Lentaris, George, Soudris, Dimitrios, Gonzalez-Arjona, David, Domingo, Ruben, Codinachs, David Merodio, Conway, Isabelle

    Published in IEEE access
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  4. 4
    EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications

    EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications by Bozzoli, Ludovica, Catanese, Antonino, Fazzoletto, Emilio, Scarpa, Eugenio, Goehringer, Diana, Pertuz, Sergio A., Kalms, Lester, Wulf, Cornelia, Charaf, Najdet, Sterpone, Luca, Azimi, Sarah, Rizzieri, Daniele, La Greca, Salvatore Gabriele, Codinachs, David Merodio, King, Stephen

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  5. 5
    Payload-XL: A Platform for the In-Orbit Validation of the BRAVE FPGA

    Payload-XL: A Platform for the In-Orbit Validation of the BRAVE FPGA by Viel, Felipe, Gouveia, Kleber R., Costa, Edilberto, Oliveira, Marcio, Boing, Miguel, Mattos, Andre Martins Pio de, Marcelino, Gabriel Mariano, Codinachs, David Merodio, Seman, Laio Oriel, Bezerra, Eduardo Augusto

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  6. 6
    Guest Editors' Introduction: Special Section on Adaptive Hardware and Systems

    Guest Editors' Introduction: Special Section on Adaptive Hardware and Systems by Benkrid, Khaled, Keymeulen, Didier, Patel, Umeshkumar D., Merodio-Codinachs, David

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  7. 7
    Experimental Validation of Fault Injection Analyses by the FLIPPER Tool

    Experimental Validation of Fault Injection Analyses by the FLIPPER Tool by Alderighi, Monica, Casini, Fabio, D'Angelo, Sergio, Mancini, Marcello, Codinachs, David Merodio, Pastore, Sandro, Poivey, Christian, Sechi, Giacomo R, Sorrenti, Gabriele, Weigand, Roland

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  8. 8
    Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices

    Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices by Portaluri, Andrea, Azimi, Sarah, De Sio, Corrado, Sterpone, Luca, Codinachs, David Merodio

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  9. 9
    BRAVE NG-MEDIUM FPGA reconfiguration through SpaceWire: example use case and performance analysis

    BRAVE NG-MEDIUM FPGA reconfiguration through SpaceWire: example use case and performance analysis by Bravhar, Klemen, Martins, Victor, Santos, Lucana, Codinachs, David Merodio

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  10. 10
    Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs

    Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs by Desogus, Marco, Sterpone, Luca, Codinachs, David Merodio

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  11. 11
    A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

    A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs by Sterpone, Luca, Azimi, Sarah, Bozzoli, Ludovica, Du, Boyang, Lange, Thomas, Glorieux, Maximilien, Alexandrescu, Dan, Polo, Cesar Boatella, Codinachs, David Merodio

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  12. 12
    Development of High-Performance DSP Algorithms on the European Rad-Hard NG-ULTRA SoC FPGA

    Development of High-Performance DSP Algorithms on the European Rad-Hard NG-ULTRA SoC FPGA by Leon, Vasileios, Xynos, Anastasios, Soudris, Dimitrios, Lentaris, George, Domingo, Ruben, Perez, Arturo, Gonzalez-Arjona, David, Conway, Isabelle, Codinachs, David Merodio

    Published in arXiv.org
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  13. 13
    Evaluation Methodology and Reconfiguration Tests on the New European NG-MEDIUM FPGA

    Evaluation Methodology and Reconfiguration Tests on the New European NG-MEDIUM FPGA by Maragos, Konstantinos, Leon, Vasileios, Lentaris, George, Soudris, Dimitrios, Gonzalez-Arjona, David, Domingo, Ruben, Pastor, Antonio, Codinachs, David Merodio, Conway, Isabelle

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  14. 14
    A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs

    A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs by Boyang Du, Sterpone, Luca, Codinachs, David Merodio

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  15. 15
    A fully-automated flow for ITAR-free rad-hard Atmel FPGAs

    A fully-automated flow for ITAR-free rad-hard Atmel FPGAs by Andrikos, Nikos, Violante, Massimo, Codinachs, David Merodio

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  16. 16
    A reliable fault classifier for dependable systems on SRAM-based FPGAs

    A reliable fault classifier for dependable systems on SRAM-based FPGAs by Bolchini, C., Sandionigi, C., Fossati, L., Codinachs, D. M.

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  17. 17
    Smart behavioral netlist simulation for SEU protection verification

    Smart behavioral netlist simulation for SEU protection verification by Schulz, S, Beltrame, G, Merodio-Codinachs, D

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  18. 18
    SerDes Integrated Into the SpaceWire Interface Helps in Achieving Higher Data Rates

    SerDes Integrated Into the SpaceWire Interface Helps in Achieving Higher Data Rates by Bravhar, Klemen, Kramberger, Iztok, Falcon, Lucana Santos, Codinachs, David Merodio, Gacnik, Dejan

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