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  1. 61
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    Transactional memory: from semantics to silicon by Adl-Tabatabai, Ali-Reza



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  2. 62
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    International workshop on multicore software engineering (IWMSE 2008) by Pankratius, Victor, Tichy, Walter F



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  3. 63
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    Engineering parallel applications with tunable architectures by Schaefer, Christoph A., Pankratius, Victor, Tichy, Walter F.



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  4. 64
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    Parallel programming: can we PLEASE get it right this time? by Mattson, Tim, Wrinn, Michael



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  5. 65
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    Automated usability evaluation of parallel programming constructs (NIER track) by Pankratius, Victor


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  6. 66
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    Sequoia: programming the memory hierarchy by Fatahalian, Kayvon, Horn, Daniel Reiter, Knight, Timothy J., Leem, Larkhoon, Houston, Mike, Park, Ji Young, Erez, Mattan, Ren, Manman, Aiken, Alex, Dally, William J., Hanrahan, Pat


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  7. 67
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    FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes by Agarwal, Rishi, Torrellas, Josep



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  8. 68
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    Multicore parallel min-cost flow algorithm for CAD applications by Lu, Yinghai, Zhou, Hai, Shang, Li, Zeng, Xuan



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  9. 69
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    Multicore software engineering: the next challenge in software engineering by Pankratius, Victor, Tichy, Walter F., Hinsbeeck, Peter



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  10. 70
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    Fourth international workshop on multicore software engineering (IWMSE 2011) by Pankratius, Victor, Philippsen, Michael



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  11. 71
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    Experiences in initiating concurrency software research efforts by Harper, K. Eric, Zheng, Jiang, Mahate, Shakeel



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  12. 72
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    A massively parallel adaptive fast-multipole method on heterogeneous architectures by Lashuk, Ilya, Chandramowlishwaran, Aparna, Langston, Harper, Nguyen, Tuan-Anh, Sampath, Rahul, Shringarpure, Aashay, Vuduc, Richard, Ying, Lexing, Zorin, Denis, Biros, George



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  13. 73
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    Distributed-memory parallel algorithms for generating massive scale-free networks using preferential attachment model by Alam, Maksudul, Khan, Maleq, Marathe, Madhav V.



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  14. 74
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    New Horizons in Multicore Software Engineering by Pankratius, Victor, Philippsen, Michael



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  15. 75
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    Enabling efficient multithreaded MPI communication through a library-based implementation of MPI endpoints by Sridharan, Srinivas, Dinan, James, Kalamkar, Dhiraj D.



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  16. 76
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    CellSs: a programming model for the cell BE architecture by Bellens, Pieter, Perez, Josep M., Badia, Rosa M., Labarta, Jesus


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  17. 77
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    Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes by Tang, Wai Teng, Tan, Wen Jun, Ray, Rajarshi, Wong, Yi Wen, Chen, Weiguang, Kuo, Shyh-hao, Goh, Rick Siow Mong, Turner, Stephen John, Wong, Weng-Fai



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  18. 78
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    Gyrokinetic toroidal simulations on leading multi- and manycore HPC systems by Madduri, Kamesh, Ibrahim, Khaled Z., Williams, Samuel, Im, Eun-Jin, Ethier, Stephane, Shalf, John, Oliker, Leonid



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  19. 79
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    Multi-core + multi-tasking = multi-opportunity? by Nyberg, Karl



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  20. 80
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    From mesh generation to scientific visualization: an end-to-end approach to parallel supercomputing by Tu, Tiankai, Yu, Hongfeng, Ramirez-Guzman, Leonardo, Bielak, Jacobo, Ghattas, Omar, Ma, Kwan-Liu, O'Hallaron, David R.


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