Search Results - Coskina, P.

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  1. 1
    Bump formation for flip chip and CSP by solder paste printing

    Bump formation for flip chip and CSP by solder paste printing by Kloeser, Joachim, Coskina, Paradiso, Aschenbrenner, Rolf, Reichl, Herbert

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  2. 2
    Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging

    Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging by Topper, M., Auersperg, J., Glaw, V., Kaskoun, K., Prack, E., Keser, B., Coskina, P., Jager, D., Fetter, D., Ehrmann, O., Samulewicz, K., Meinherz, C., Fehlberg, S., Karduck, C., Reichl, H.

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  3. 3
    Lead free alloys for flip chip bumping

    Lead free alloys for flip chip bumping by Jung, E., Aschenbrenner, R., Kallmayer, C., Coskina, P., Reichl, H.

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  4. 4
    Wafer-level chip size package (WL-CSP)

    Wafer-level chip size package (WL-CSP) by Topper, M., Fehlberg, S., Scherpinski, K., Karduck, C., Glaw, V., Heinricht, K., Coskina, P., Ehrmann, O., Reichl, H.

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  5. 5
    Numerical and experimental investigations of large IC flip chip attach

    Numerical and experimental investigations of large IC flip chip attach by Schubert, A., Dudek, R., Leutenbauer, R., Coskina, P., Becker, K.-F., Kloeser, J., Michel, B., Reichl, H., Baldwin, D., Qu, J., Sitaraman, S., Wong, C.P., Tummala, R.

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  6. 6
    Wafer level package using double balls

    Wafer level package using double balls by Topper, M., Glaw, V., Coskina, P., Auersperg, J., Samulewicz, K., Lange, M., Karduck, C., Fehlberg, S., Ehrmann, O., Reichl, H.

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