Search Results - Dadian Zhou

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  1. 1
    A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test

    A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test by Chen, Tao, Park, Chulhyun, Meng, Hao, Zhou, Dadian, Silva-Martinez, Jose, Geiger, Randall L., Chen, Degang

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  2. 2
    A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

    A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration by Dadian Zhou, Briseno-Vidrios, Carlos, Junning Jiang, Chulhyun Park, Qiyuan Liu, Soenen, Eric G., Kinyua, Martin, Silva-Martinez, Jose

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  3. 3
    Recent Advances on Linear Low-Dropout Regulators

    Recent Advances on Linear Low-Dropout Regulators by Silva-Martinez, Jose, Liu, Xiaosen, Zhou, Dadian

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  4. 4
    A 200MSPS time-interleaved 12-bit ADC system with digital calibration

    A 200MSPS time-interleaved 12-bit ADC system with digital calibration by Bommireddipalli, Aditya, Dadian Zhou, Talarico, Claudio, Silva-Martinez, Jose, Karsilayan, Aydin I.

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  5. 5
    Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs

    Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs by Hassan, Amr W., Zhou, Dadian, Silva-Martinez, Jose

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  6. 6
    A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator

    A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator by Zhou, Dadian, Jiang, Junning, Liu, Qiyuan, Soenen, Eric G., Kinyua, Martin, Silva-Martinez, Jose

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  7. 7
    A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS

    A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS by Liu, Qiyuan, Edward, Alexander, Zhou, Dadian, Silva-Martinez, Jose

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  8. 8
    A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs

    A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs by Briseno-Vidrios, Carlos, Zhou, Dadian, Prakash, Suraj, Liu, Qiyuan, Edward, Alexander, Soenen, Eric G., Kinyua, Martin, Silva-Martinez, Jose

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  9. 9
    A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration

    A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration by Dadian Zhou, Talarico, Claudio, Silva-Martinez, Jose

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  10. 10
    A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier

    A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier by Park, Chulhyun, Chen, Tao, Noh, Kyoohyun, Zhou, Dadian, Prakash, Suraj, Alizadeh, Mohammadhossein Naderi, Karsilayan, Aydin I., Chen, Degang, Geiger, Randall L., Silva-Martinez, Jose

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  11. 11
    A 2.3-3.9 GHz Fractional-N Frequency Synthesizer with Charge Pump and TDC Calibration for Reduced Reference and Fractional Spurs

    A 2.3-3.9 GHz Fractional-N Frequency Synthesizer with Charge Pump and TDC Calibration for Reduced Reference and Fractional Spurs by Jiang, Junning, Yan, Tanwei, Zhou, Dadian, Karsilayan, Aydin Ilker, Silva-Martinez, Jose

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